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| features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 124 powerful instructions - most single clock cycle execution ? 32 x 8 general purpose working registers ? fully static operation ? up to 8 mips throughput at 8 mhz ? high endurance non-volatile memory segments ? 16k/32k bytes of in-system self-programmable flash (atmega16hvb/32hvb) ? 512/1k bytes eeprom ? 1k/2k bytes internal sram ? write/erase cycles 10, 000 flash/100,000 eeprom ? data retention: 20 years at 85c/100 years at 25c (1) ? optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-write operation ? programming lock for software security ? battery management features ? two, three or four cells in series ? high-current protection (charge and discharge) ? over-current protection (charge and discharge) ? short-circuit protection (discharge) ? high voltage outputs to drive n-channel charge/discharge fets ? optional deep under voltage recovery mo de - allowing 0-volt charging without external precharge fet ? optional high voltage open drain ouput - allowing 0-volt charging with external precharge fet ? integrated cell balancing fets ? peripheral features ? two configurable 8- or 16-bit timers with separate prescaler, optional input capture (ic), compare mode and ctc ? spi - serial peripheral interface ? 12-bit voltage adc, six external and one internal adc input ? high resolution coulomb counter adc for current measurements ? twi serial interface supporting smbus implementation ? programmable watchdog timer ? special microcontroller features ? debugwire on-chip debug system ? in-system programmable via spi ports ?power-on reset ? on-chip voltage regulator with short-circuit monitoring interface ? external and internal interrupt sources ? sleep modes: idle, adc noise redu ction, power-save, and power-off ? additional secure authentication features available only under nda ? packages ? 44-pin tssop ? operating voltage: 4 - 25v ? maximum withstand voltage (high-voltage pins): 35v ? temperature range: -40c to 85c ? speed grade: 1-8 mhz note: 1. see ?data retention? on page 8 for details. 8-bit microcontroller with 16k/32k bytes in-system programmable flash atmega16hvb atmega32hvb preliminary 8042a?avr?07/09
2 8042a?avr?07/09 atmega16hvb/32hvb 1. pin configurations 1.1 tssop figure 1-1. tssop - pinout atmega16hvb/32hvb 1.2 pin descriptions 1.2.1 vfet high voltage supply pin. this pin is used as suppl y for the internal voltage regulator, described in ?voltage regulator? on page 132 . 1.2.2 vclmp10 internal 10v clamping of vfet voltage for external decoupling. 1.2.3 vcc digital supply voltage. no rmally connected to vreg. 1 44 3 pi ppi nv pv1 pv2 pv3 pv4 pvt vcc gnd pc5 pc4(scl) pc3(int3/sda) pc2(int2) pc1(int1) pc0(int0/extprot) pb7(miso/pcint11) nc pb6(mosi/pcint10) pb5(sck/pcint9) pb4(ss/pcint8) pb3(pcint7) 2 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 21 22 4 3 42 41 40 3 9 38 3 7 3 6 3 5 3 4 33 3 2 3 1 3 0 29 2 8 27 26 25 24 2 3 ni nni vrefgnd vref gnd vreg pa0(adc0/sgnd/pcint0) pa1(adc1/sgnd/pcint1) pa2(pcint2/t0) pa3(pcint3/t1) vclmp10 vfet batt vcc gnd od nc oc reset/dw pb0(pcint4/icp00) pb1(pcint5/ckout) pb2(pcint6) 3 8042a?avr?07/09 atmega16hvb/32hvb 1.2.4 vreg output from the internal voltage regulator. used for external decoupling to ensure stable regu- lator operation. for details, see ?voltage regulator? on page 132 . 1.2.5 vref internal voltage reference for external decoupling. for details, see ?voltage reference and temperature sensor? on page 123 . 1.2.6 vrefgnd ground for decoupling of internal voltage reference. for details, see ?voltage reference and temperature sensor? on page 123 . do not connect to gnd or sgnd on pcb. 1.2.7 gnd ground 1.2.8 port a (pa3..pa0) port a serves as a low-voltage 4-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). as inputs, port a pins that are externally pulled low will source current if the pull-up resistors are activated. the port a pins are tri-stated when a reset condition becomes active, even if the clock is not running. port a also serves the functions of various special features of the atmega16hvb/32hvb as listed in ?alternate functions of port a? on page 74 . 1.2.9 port b (pb7..pb0) port b is a low-voltage 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). as inputs, port b pins that are exter nally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. port b also serves the functions of various special features of the atmega16hvb/32hvb as listed in ?alternate functions of port b? on page 75 . 1.2.10 port c (pc5) port c (pc5) is a high voltage open drain output port. 1.2.11 port c (pc4..pc0) port c is a 5-bit high voltage open drain bi-directional i/o port. 1.2.12 oc/od high voltage output to drive charge/discharge fet. for details, see ?fet driver? on page 148 . 1.2.13 pi/ni filtered positive/negative input from external cu rrent sense resistor, used to by the coulomb counter adc to measure charge/discharge currents flowing in the battery pack. for details, see ?coulomb counter - dedicated fuel gauging sigma-delta adc? on page 108 . 4 8042a?avr?07/09 atmega16hvb/32hvb 1.2.14 ppi/nni unfiltered positive/negative input from external current sense resistor, used by the battery pro- tection circuit, for over-current and short-circuit detection. for details, see ?battery protection? on page 135 . 1.2.15 nv/pv1/pv2/pv3/pv4 nv, pv1, pv2, pv3, and pv4 are the inputs for battery cells 1, 2, 3 and 4, used by the voltage adc to measure each cell voltage. for details, see ?voltage adc ? 7-channel general purpose 12-bit sigma-delta adc? on page 117 . 1.2.16 pvt defines the source voltage level for the charge fet driver. for details, see ?fet driver? on page 148 . 1.2.17 batt input for detecting when a charger is connected. defines the source voltage level for the dis- charge fet driver. for details, see ?fet driver? on page 148 . 1.2.18 reset /dw reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in table 11 on page 38. shorter pulses are not guaranteed to generate a reset. this pin is also used as debugwire communication pin. 5 8042a?avr?07/09 atmega16hvb/32hvb 2. overview the atmega16hvb/32hvb is a monitoring and protection circuit for 3 and 4-cell li-ion applica- tions with focus on highest safety including safe authentication, low co st and high utilization of the cell energy. the device contains secure authentication features as well as autonomous bat- tery protection during charging and discharging. the external protection input can be used to implement other battery protection mechanisms using external components, e.g. protection against chargers with too high charge voltage can be easily implemented with a few low cost passive components. the feature set makes the atmega16hvb/32hvb a key component in any system focusing on high secu rity, battery protection, high system utilization and low cost. figure 2-1. block diagram atmega16hvb/32hvb provides the necessary redundancy on-chip to make sure that the bat- tery is protected in critical failure modes. the chip is specifically designed to provide safety for the battery cells in case of pin shorting, loss of power (either caused by battery pack short or porta (4) sram flash cpu eeprom pv2 nv oc fet control voltage adc voltage reference coulomb counter adc gnd vcc reset/dw power supervision por & reset watchdog oscillator watchdog timer oscillator circuits / clock generation vref vrefgnd pi ni pa3..0 pa1..0 8/16-bit t/c1 8/16-bit t/c0 portb (8) pb7..0 spi voltage regulator charger detect vfet vreg batt pv1 data b u s v p tat current protection security module portc (6) pc5..0 voltage regulator monitor interface pb0 oscillator sampling interface program logic debugwire cell balancing pv3 pv4 twi ppi nni od porta (4) sram flash cpu eeprom pv2 nv oc fet control voltage adc voltage reference coulomb counter adc gnd vcc reset/dw power supervision por & reset watchdog oscillator watchdog timer oscillator circuits / clock generation vref vrefgnd pi ni pa3..0 pa1..0 8/16-bit t/c1 8/16-bit t/c0 portb (8) pb7..0 spi voltage regulator charger detect vfet vreg batt pv1 data b u s v p tat current protection security module portc (6) pc5..0 voltage regulator monitor interface pb0 oscillator sampling interface program logic debugwire cell balancing pv3 pv4 twi ppi nni od 6 8042a?avr?07/09 atmega16hvb/32hvb vcc short), illegal charger conne ction or software runaway. this make s atmega16hvb/32hvb the ideal 1-chip solution for applications with focus on high safety. the atmega16hvb/32hvb features an integrated voltage regulator that operates at a wide range of input voltages, 4 - 25 volts. this voltage is regulated to a constant supply voltage of nominally 3.3 volts for the integr ated logic and analog functions. the regulator capabilities, com- bined with an extremely low power consumption in the power saving modes, greatly enhances the cell energy utilization compared to existing solutions. the chip utilizes atmel's patented deep under-voltage recovery (duvr) mode that supports pre-charging of deeply discharged battery cells without using a separate pre-charge fet. optionally, pre-charge fets are supported for integration into many existing battery charging schemes. the battery protection monitors the charge and dischar ge current to detect illegal conditions and protect the battery from these when required. a 12-bit voltage adc allows software to monitor each cell voltage individually with high accuracy. the adc also provides one internal input chan- nel to measure on-chip temperature and two i nput channels intended for external thermistors. an 18-bit adc optimized for coulomb counting accumulates charge and discharge currents and reports accumulated current with high resoluti on and accuracy. it can also be used to provide instantaneous current measurements with 13 bit resolution. integrated cell balancing fets allow cell balancing algorithms to be implemented in software. the mcu provides the following features: 16k/32k bytes of in-system programmable flash with read-while-write capabilities, 512/1k bytes eeprom, 1k/2k by tes sram. 32 general purpose working registers, 12 general purpose i/o lines, 5 general purpose high voltage open drain i/o lines, one general purpose super high voltage open drain output, debugwire for on-chip debugging and spi for in-system programming, a sm-bus comp liant twi module, two flexible timer/counters with input capture and compare modes. internal and external interrupts, a 12-bit sigma delta adc for voltage and temperature measure- ments, a high resolution sigma delta adc for coulomb counting and instantaneous current measurements, integrated cell balancing fets, additional secure authentication features, an autonomous battery protection m odule, a programmable watchdog timer with internal oscilla- tor, and software selectable power saving modes. the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional cisc microcontrollers. the device is manufactured using atmel?s high voltage high density non-volatile memory tech- nology. the on-chip isp flash allows the program memory to be reprogrammed in-system, through an spi serial interface, by a conventiona l non-volatile memory programmer or by an on- chip boot program running on the avr core. the boot program can use any interface to down- load the application program in the application flash memory. software in the boot flash section will continue to run while the applicati on flash section is updated, providing true read- while-write operation. by combining an 8-bit risc cpu with in-system self-programmable- flash and highly accurate analog front-end in a monolithic chip. the atmel atmega16hvb/32hvb is a powerful microcontroller that provides a highly flexible and cost effective solution. it is part of the avr battery management family that provides secure 7 8042a?avr?07/09 atmega16hvb/32hvb authentication, highly accurate monitoring and autonomous protection for lithium-ion battery cells. the atmega16hvb/32hvb avr is supported with a full suite of program and system develop- ment tools including: c compilers, macro assemblers, program debugger/simulators, and on- chip debugger. 2.1 comparison between atmega16hvb and atmega32hvb the atmega16hvb and atmega32hvb differ only in memory size for flash, eeprom and internal sram. table 2-1 summarizes the different conf iguration for the two devices. table 2-1. configuration summary device flash eeprom sram atmega16hvb 16k 512 1k atmega32hvb 32k 1k 2k 8 8042a?avr?07/09 atmega16hvb/32hvb 3. disclaimer all parameters contained in this datasheet ar e preliminary and based on characterization of atmega16/32hvb. 4. resources a comprehensive set of development tools, app lication notes and datasheets are available for download on http:// www.atmel.com/avr.n1 note: 1. 5. about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ?sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructio ns that allow access to extended i/o. typically ?lds? and ?sts? combined with ? sbrs?, ?sbrc?, ?sbr?, and ?cbr?. 6. data retention reliability qualification results show that the pr ojected data retention failure rate is much less than 1 ppm over 20 years at 85c or 100 years at 25c. 9 8042a?avr?07/09 atmega16hvb/32hvb 7. avr cpu core 7.1 overview this section discusses the avr core architecture in general. the main function of the cpu core is to ensure correct program execution. the cpu must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. figure 7-1. block diagram of the avr architecture in order to maximize performance and parallelism, the avr uses a harvard architecture ? with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipelining. while one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the program memory is in-system reprogrammable flash memory. the fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. this allows single-cycle ar ithmetic logic unit (alu ) operation. in a typ- flash program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu status and control i/o lines eeprom data bus 8-bit data sram direct addressing indirect addressing interrupt unit watchdog timer i/o module 2 i/o module1 i/o module n 10 8042a?avr?07/09 atmega16hvb/32hvb ical alu operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-b it indirect address register pointers for data space addressing ? enabling efficient address calculations. one of the these address pointers can also be used as an address pointer for look up tables in flash program memory. these added function registers are the 16-bit x-, y-, and z-register, described later in this section. the alu supports arithmetic and logic operations between registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic opera- tion, the status register is updated to reflect information about the result of the operation. program flow is provided by conditional and uncon ditional jump and call instructions, able to directly address the whole address space. most avr instructions have a single 16-bit word for- mat. every program memory address contains a 16- or 32-bit instruction. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram, and consequently the stack size is only limited by the to tal sram size and the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the stack pointer (sp) is read/write accessible in the i/o space. the data sram can easily be accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control r egisters in the i/o space with an additional global interrupt enable bit in the status register. all interrupts have a separate interrupt vector in the interrupt vector table. the interrupts have priority in accordance with their interrupt vector posi- tion. the lower the interrupt vector address, the higher the priority. the i/o memory space contains 64 addresses for cpu peripheral functi ons as control regis- ters, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5f. in addition, the atmega16hvb/32hvb has extended i/o space from 0x60 - 0xff in sram where only the st/sts/std and ld/lds/ldd instructions can be used. 7.2 alu ? arithm etic logic unit the high-performance avr alu operates in dire ct connection with all the 32 general purpose working registers. within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. the alu operations are divided into three main categories ? arithmetic, logical, and bit-functions. some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. see the ?instruction set? section for a detailed description. 7.3 status register the status register contains information about the result of the most recently executed arithme- tic instruction. this information can be used for altering program flow in order to perform conditional operations. note that the status register is updated after all alu operations, as specified in the instruction set reference. this will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. this must be handled by software. 11 8042a?avr?07/09 atmega16hvb/32hvb 7.3.1 sreg ? avr status register ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set for th e interrupts to be enabled. the individual inter- rupt enable control is then performed in separate control registers. if the global interrupt enable register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. the i-bit can also be set and cleared by the application with the sei and cli instructions, as described in the instruction set reference. ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (b it store) use the t-bit as source or desti- nation for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag h indicates a half carry in so me arithmetic operations. half carry is useful in bcd arithmetic. see the ?instruction set description? for detailed information. ? bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative flag n and the two?s complement overflow flag v. see the ?instruction set description? for detailed information. ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v suppor ts two?s complement arithmetics. see the ?instruction set description? for detailed information. ? bit 2 ? n: negative flag the negative flag n indicates a negative result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. ? bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see the ?instruction set description? for de tailed information. bit 76543210 0x3f (0x5f) i t h s v n z c sreg read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 12 8042a?avr?07/09 atmega16hvb/32hvb 7.4 general purpose register file the register file is optimized for the avr enhanc ed risc instruction set. in order to achieve the required performance and flex ibility, the following in put/output schemes ar e supported by the register file: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? two 8-bit output operands and one 16-bit result input ? one 16-bit output operand and one 16-bit result input figure 7-2 shows the structure of the 32 general purpose working registers in the cpu. figure 7-2. avr cpu general purpose working registers most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions. as shown in figure 7-2 , each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. although not being physically imple- mented as sram locations, this memory organization provides great flexibility in access of the registers, as the x-, y- and z-pointer registers can be set to index any register in the file. 7.4.1 the x-register, y-register, and z-register the registers r26..r31 have some added functions to their general purpose usage. these reg- isters are 16-bit address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as described in figure 7-3 on page 13 . 70addr. r0 0x00 r1 0x01 r2 0x02 ? r13 0x0d general r14 0x0e purpose r15 0x0f working r16 0x10 registers r17 0x11 ? r26 0x1a x-register low byte r27 0x1b x-register high byte r28 0x1c y-register low byte r29 0x1d y-register high byte r30 0x1e z-register low byte r31 0x1f z-register high byte 13 8042a?avr?07/09 atmega16hvb/32hvb figure 7-3. the x-, y-, and z-registers in the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 7.5 stack pointer the stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. the stack pointer register always points to the top of the stack. note that the stack is implemented as growing from higher memory loca- tions to lower memory locations. this implies that a stack push command decreases the stack pointer. the stack pointer points to the data sram stack area where the subroutine and interrupt stacks are located. this stack space in the data sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. the stack pointer must be set to point above 0x100. the stack pointer is decremented by one when data is pushed onto the stack with the push instruction, and it is decremented by two when the return address is pushed onto the stack with subroutine call or interrupt. the stack pointer is incremented by one when data is popped from the stack with the pop instruction, and it is incremented by two when data is popped from the stack with return from subroutine ret or return from interrupt reti. the avr stack pointer is implemented as two 8- bit registers in the i/o space. the number of bits actually used is implementation dependent. note that the data space in some implementa- tions of the avr architecture is so small that only spl is needed. in this case, the sph register will not be present. 7.5.1 sph and spl ? stack pointer high and stack pointer low 15 xh xl 0 x-register 707 0 r27 (0x1b) r26 (0x1a) 15 yh yl 0 y-register 707 0 r29 (0x1d) r28 (0x1c) 15 zh zl 0 z-register 7070 r31 (0x1f) r30 (0x1e) bit 151413121110 9 8 0x3e (0x5e) sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph 0x3d (0x5d) sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 00000000 14 8042a?avr?07/09 atmega16hvb/32hvb 7.6 instruction execution timing this section describes the general access timi ng concepts for instruction execution. the avr cpu is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal clo ck division is used. figure 7-4 shows the parallel instruction fetches and instruction executions enabled by the har- vard architecture and the fast-access register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz with the corr esponding unique results for functions per cost, functions per clocks, and functions per power-unit. figure 7-4. the parallel instruction fetches and instruction executions figure 7-5 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destina- tion register. figure 7-5. single cycle alu operation 7.7 reset and inte rrupt handling the avr provides several different interrupt sources. these interrupts and the separate reset vector each have a separate program vector in the program memory space. all interrupts are assigned individual enable bits which must be written logic one together with the global interrupt enable bit in the status register in order to enable the interrupt. the lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. the complete list of vectors is shown in ?interrupts? on page 52 . the list also determines the priority levels of the different interrupts. the lower the address the higher is the priority level. reset ha s the highest priority. clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 cpu total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 clk cpu 15 8042a?avr?07/09 atmega16hvb/32hvb when an interrupt occurs, the global interrupt enable i-bit is cleared and all interrupts are dis- abled. the user software can write logic one to the i-bit to enable nested interrupts. all enabled interrupts can then interrupt the current interrupt routine. the i-bit is automatically set when a return from interrupt instruction ? reti ? is executed. there are basically two types of interrupts. the fi rst type is triggered by an event that sets the interrupt flag. for these interrupts, the program counter is vectored to the actual interrupt vector in order to execute the interrupt handling rout ine, and hardware clears the corresponding inter- rupt flag. interrupt flags can also be cleared by wr iting a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and re membered until the inte rrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt condit ions occur while the global interrupt enable bit is cleared, the corresponding interrupt flag(s) w ill be set and remembered until the global interrupt enable bit is set, and will th en be executed by order of priority. the second type of interrupts will trigger as long as the interrupt condition is present. these interrupts do not necessarily have interrupt flags. if the interrupt condition disappears before the interrupt is enabled, the in terrupt will not be triggered. when the avr exits from an inte rrupt, it will always retu rn to the main pr ogram and execute one more instruction before any pending interrupt is served. note that the status register is not automatica lly stored when entering an interrupt routine, nor restored when returning from an interrupt routine. this must be handled by software. when using the cli instruction to disable interrupts, the interrup ts will be immediately disabled. no interrupt will be executed af ter the cli instruction, even if it occurs simultaneously with the cli instruction. the following example shows how this can be used to avoid interrupts during the timed eeprom write sequence. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eempe ; start eeprom write sbi eecr, eepe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ _cli(); eecr |= (1< 17 8042a?avr?07/09 atmega16hvb/32hvb 8. avr memories 8.1 overview this section describes the different memories in the atmega16hvb/32hvb. the avr architec- ture has two main memory spaces, the data memory and the program memory space. in addition, the atmega16hvb/32hvb features an eeprom memory for data storage. all three memory spaces are linear and regular. 8.2 in-system reprogrammable flash program memory the atmega16hvb/32hvb contains 16k/32k by tes on-chip in-system reprogrammable flash memory for program storage. since all avr instructions are 16 or 32 bits wide, the flash is orga- nized as 8k/16k x 16. the flash memory has an endurance of at least 10,000 write/erase cycles. the atmega16hvb/32hvb program counter (pc) is 13/14 bits wide, thus addressing the 8k/16k program memory locations. the operation of boot program section and associated boot lock bits for software protection are described in detail in ?boot loader support ? read-while-write self-programming? on page 191 . ?memory programming? on page 208 contains a detailed description on flash programming. constant tables can be allocated within the entire program memory address space (see the lpm ? load program memory instruction description). timing diagrams for instruction fetch and execution are presented in ?instruction execution tim- ing? on page 14 . figure 8-1. program memory map 8.3 sram data memory figure 8-2 on page 18 shows how the atmega16hvb/32hvb sram memory is organized. 0x0000 0x1fff/0x3fff program memory application flash section boot flash section 18 8042a?avr?07/09 atmega16hvb/32hvb the atmega16hvb/32hvb is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. the lower 1280/2304 data memory locations address both the register file, the i/o memory, extended i/o memory, and the internal data sr am. the first 32 locations address the register file, the next 64 location the standard i/o memory, then 160 locations of extended i/o memory, and the next 1k/2k locations address the internal data sram. the five different addressing modes for the data memory cover: direct, indirect with displace- ment, indirect, indirect with pre-decrement, and indirect with post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space. the indirect with displacement mode reaches 63 address locations from the base address given by the y- or z-register. when using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers x, y, and z are decremented or incremented. the 32 general purpose working registers, 64 i /o registers, 160 extended i/o registers, and the 1k/2k bytes of internal data sram in the atmega16hvb/32hvb are all accessible through all these addressing modes. the register file is described in ?general purpose register file? on page 12 . figure 8-2. data memory map 8.3.1 data memory access times this section describes the general access timi ng concepts for internal memory access. the internal data sram access is performed in two clk cpu cycles as described in figure 8-3 . 32 registers 64 i/o registers internal sram (1k/2k x 8) 0x0000 - 0x001f 0x0020 - 0x005f 0x04ff/0x08ff 0x0060 - 0x00ff data memory 160 ext i/o reg. 0x0100 19 8042a?avr?07/09 atmega16hvb/32hvb figure 8-3. on-chip data sram access cycles 8.4 eeprom data memory the atmega16hvb/32hvb contains 512/1k bytes of data eeprom memory. it is organized as a separate data space, in which single bytes can be read and written. the eeprom has an endurance of at least 100,000 write/erase cycles. the access between the eeprom and the cpu is described in the following, specif ying the eeprom address registers, the eeprom data register, and the eeprom control register. for a detailed description of eeprom programming, see page 211 and page 216 respectively. 8.4.1 eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access time for the eeprom is given in table 8-1 on page 21 . a self-timing function, however, lets the user software detect when the nex t byte can be written. if the user code con- tains instructions that write the eeprom, some precautions must be taken. in order to prevent unintentional eeprom writes, a specific write procedure must be followed. refer to the description of the eeprom control regist er for details on this. when the eeprom is read, the cpu is halted for fo ur clock cycles before the next in struction is executed. when the eeprom is written, the cp u is halted for two clock cycles before the next instruction is executed. 8.5 i/o memory the i/o space definition of the atmega16hvb/32hvb is shown in ?register summary? on page 254 . all atmega16hvb/32hvb i/os and peripherals are placed in the i/o space. all i/o locations may be accessed by the ld/lds/ldd and st/sts/std instructions, transferring data between the 32 general purpose working registers and the i/o space. i/o registers within the address range 0x00 - 0x1f are directly bit-accessible us ing the sbi and cbi instructions. in these regis- ters, the value of single bits can be checked by using the sbis and sbic instructions. refer to the instruction set section for more details. when using the i/o specific commands in and out, clk wr rd data data address address valid t1 t2 t3 compute address read write cpu memory access instruction next instruction 20 8042a?avr?07/09 atmega16hvb/32hvb the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the atmega16hvb/32hvb is a complex microcontroller with more peripheral units than can be sup- ported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instruc- tions can be used. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory addresses should never be written. some of the status flags are cleared by writing a logical one to them. note that the cbi and sbi instructions will only oper ate on the specified bit, and can th erefore be used on registers contain- ing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. the i/o and peripherals control registers are explained in later sections. 8.5.1 general purpose i/o registers the atmega16hvb/32hvb contains three general purpose i/o registers. these registers can be used for storing any information, and they are particularly useful for storing global variables and status flags. general purpose i/o registers within the address range 0x00 - 0x1f are directly bit-accessible using the sbi, cbi, sbis, and sbic instructions. 8.6 register description 8.6.1 eearh and eearl? the eeprom address register high and low ? bits 15:10 ? res: reserved bits these bits are reserved bits in the atme ga16hvb/32hvb and will always read as zero. ? bits 9:0 ? eear9:0: eeprom address the eeprom address registers ? eear specif y the eeprom address in the 512/1k bytes eeprom space. the eeprom data bytes are addressed linearly between 0 and 511/1023. the initial value of eear is undefined. a proper value must be written before the eeprom may be accessed. 8.6.2 eedr ? the eeprom data register bit 151413121110 9 8 0x22 (0x42) eear9 eear8 eearh 0x21 (0x41) eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl bit 76543210 read/write rrrrrrr/wr/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 x x xxxxxxxx bit 76543210 0x20 (0x40) msb lsb eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 21 8042a?avr?07/09 atmega16hvb/32hvb ? bits 7:0 ? eedr7:0: eeprom data for the eeprom write operation, the eedr register contains the data to be written to the eeprom in the address given by the eear regi ster. for the eeprom read operation, the eedr contains the data read out from the eeprom at the add ress given by eear. 8.6.3 eecr ? the eeprom control register ? bits 7:6 ? res: reserved bits these bits are reserved bits in the atme ga16hvb/32hvb and will always read as zero. ? bits 5, 4 ? eepm1 and eepm0: eeprom programming mode bits the eeprom programming mode bit setting define s which programming acti on that will be trig- gered when writing eepe. it is possible to program data in one atomic operation (erase the old value and program the new value) or to split the erase and write operations in two different operations. the programming times for the different modes are shown in table 8-1 . while eepe is set, any write to eepmn will be ignored. du ring reset, the eepmn bits will be reset to 0b00 unless the eeprom is busy programming. note: 1. actual timing depends on frequency of the calibrated fast rc oscillator. ? bit 3 ? eerie: eeprom ready interrupt enable writing eerie to one enables the eeprom ready interrupt if the i bit in sreg is set. writing eerie to zero disables the interrupt. the eeprom ready interrupt generates a constant inter- rupt when eepe is cleared. ? bit 2 ? eempe: eeprom master write enable the eempe bit determines whether setting eepe to one causes the eeprom to be written. when eempe is set, setting eepe within four cloc k cycles will write data to the eeprom at the selected address if eempe is zero, setting eepe will have no effect. when eempe has been written to one by software, ha rdware clears the bit to zero after four clock cycles. see the description of the eepe bit fo r an eeprom write procedure. ? bit 1 ? eepe: eeprom write enable the eeprom write enable signal eepe is the wr ite strobe to the eeprom. when address and data are correctly set up, the eepe bit must be written to one to write the value into the bit 76543 210 0x1f (0x3f) ? ? eepm1 eepm0 eerie eempe eepe eere eecr read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 x x 0 0 x 0 table 8-1. eeprom mode bits eepm1 eepm0 typ. programming time (1) operation 0 0 3.4 ms erase and write in one operation (atomic operation) 0 1 1.8 ms erase only 1 0 1.8 ms write only 1 1 ? reserved for future use 22 8042a?avr?07/09 atmega16hvb/32hvb eeprom. the eempe bit must be written to one be fore a logical one is written to eepe, other- wise no eeprom write takes pl ace. the following pr ocedure should be followed when writing the eeprom (the order of steps 2 and 3 is not essential): 1. wait until eepe becomes zero. 2. write new eeprom address to eear (optional). 3. write new eeprom data to eedr (optional). 4. write a logical one to the eempe bit while writing a zero to eepe in eecr. 5. within four clock cycles after settin g eempe, write a logical one to eepe. caution: an interrupt betwe en step 4 and step 5 will make the wr ite cycle fail, since the eeprom master write enable will time-out. if an interrupt routine ac cessing the eeprom is interrupting another eeprom access, the eear or eedr register will be modified, causing the interrupted eeprom access to fail. it is recommended to have the global interrupt flag cleared during all the steps to avoid these problems. when the write access time has elapsed, the ee pe bit is cleared by hardware. the user soft- ware can poll this bit and wait for a zero before writing the next byte. when eepe has been set, the cpu is halted for two cycles before the next instruction is executed. caution: a bod reset during eeprom writ e will invalidate the result of the ongoing operation. ? bit 0 ? eere: eeprom read enable the eeprom read enable signal eere is the re ad strobe to the eeprom. when the correct address is set up in the eear register, the eere bit must be written to a logic one to trigger the eeprom read. the eeprom read access takes one instruction, and th e requested data is available immediately. when t he eeprom is read, the cpu is ha lted for four cycles before the next instruction is executed. the user should poll the eepe bit before starting the read operation. if a write operation is in progress, it is neither possi ble to read the eeprom, nor to change the eear register. the calibrated oscillator is used to time t he eeprom accesses and the programming time will therefore depend on the calib rated oscillator frequency. table 8-2 lists the typical programming time for eeprom access from the cpu. the following code examples show one assembly and one c function for writing to the eeprom. the examples assume that interrupts are controlled (e.g. by dis abling interrupts glob- ally) so that no interrupts will occur during ex ecution of these functions. the examples also assume that no flash boot loader is present in the software. if such code is present, the eeprom write function must also wait fo r any ongoing spm co mmand to finish. table 8-2. eeprom programming time symbol number of calibrated rc oscillator cycles typ programming time, f osc = 8 mhz eeprom write (from cpu) 27200 3.4 ms 23 8042a?avr?07/09 atmega16hvb/32hvb the next code examples show assembly and c functions for reading the eeprom. the exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. assembly code example eeprom_write: ; wait for completion of previous write sbic eecr,eepe rjmp eeprom_write ; set up address (r18:r17) in address register out eearh, r18 out eearl, r17 ; write data (r16) to data register out eedr,r16 ; write logical one to eempe sbi eecr,eempe ; start eeprom write by setting eepe sbi eecr,eepe ret c code example void eeprom_write( unsigned int uiaddress, unsigned char ucdata) { /* wait for completion of previous write */ while(eecr & (1< 26 8042a?avr?07/09 atmega16hvb/32hvb 9.1.4 voltage adc clock ? clk vadc the voltage adc is provided with a dedicated clock domain. the vadc clock is automatically prescaled relative to the system clock prescalers setting by the vadc prescaler, giving a fixed vadc clock at 1 mhz. 9.1.5 coulomb counter adc clock - clk ccadc the coulomb counter adc is provided with a dedic ated clock domain. this allows operating the coulomb counter adc in low power modes like power-save for continuous current measurements. 9.1.6 watchdog timer and battery protection clock the watchdog timer and battery protection are provided with a dedicated clock domain. this allows operation in all modes exce pt power-off. it also allows ve ry low power operation by utiliz- ing an ultra low power rc oscilla tor dedicated to this purpose. 9.2 clock sources the following section describes the clock sources available in the device. the clocks are input to the avr clock generator, and routed to the appropriate modules. the atmega16hvb/32 hvb has 3 on-board osc illator used to clock the internal logic. table 9-1 shows the clock sources and their usage. 9.2.1 calibrated fast rc oscillator the calibrated fast rc oscillator by default provides a 8.0 mhz cl ock. the frequency is nominal value at 25 c. this clock will operate with no ex ternal components. during reset, hardware loads the calibration byte into the fosccal register and thereby automatically calibrates the fast rc oscillator. at 25 c, this calibration gives a frequen cy of 8 mhz 1%. the oscillator can be calibrated to any frequency in the range 7.3 - 8.1 mhz by changing the fosccal register. for more information on the pre-programmed calibration value, see the section ?reading the signature row from software? on page 199 . note that the frequency of the system clock is given by the ?system clock prescaler? on page 28 . table 9-1. available clock sources. clock source usage calibrated fast rc oscillator the clock source for the cpu, i/o, flash, and voltage adc. ultra low power rc oscillator the clock source for the watchd og timer, battery protection, coulomb counter adc, bandgap buffer short circuit detector, and smbus connect/disconnect. slow rc oscillator used by the oscillator sampling interface (osi). 27 8042a?avr?07/09 atmega16hvb/32hvb when this oscillator is select ed, start-up times are determined by the sut fuses as shown in table 9-2 on page 27 . notes: 1. the device is shipped with this option selected. 2. the actual value of the added, selectable 4- 512 ms delay depends on the actual frequency of the ?ultra low power rc oscillator? on page 27 . see table 9-3 on page 28 and ?electrical characteristics? on page 228 9.2.2 slow rc oscillator the slow rc oscillator provides a 131 khz clock (typical value, refer to section ?electrical char- acteristics? on page 228 ). this clock can be used as a timing reference for run-time calibration of the fast rc oscillator and for ac curately determining t he actual ulp oscillator frequency, refer to ?osi ? oscillator sampling interface? on page 29 for details. to provide good accuracy when used as a timing re ference, the slow rc oscillator has calibra- tion bytes stored in the signature address space, refer to section ?reading the signature row from software? on page 199 for details. the actual clock peri od of the slow rc oscillator in s as a function of temperature is given by: where t is the die temperature in kelvin and t hot is the calibration temperature stored in the sig- nature row. the die temperature can be found using the voltage adc, refer to section ?voltage adc ? 7-channel general purpose 12-bit sigma-delta adc? on page 117 for details. 9.2.3 ultra low power rc oscillator the ultra low power rc oscillator (ulp oscill ator) provides a 128 khz clock (typical value, refer to section ?electrical characteristics? on page 228 ). this oscillator provides the clock for the watchdog timer and battery protection m odules. the actual ulp oscillator frequency depends on process variations and temperature, see ?electrical characteristics? on page 228 . the oscillator is automatically en abled in all operational modes. it is also enab led during reset. there are two altern ative methods for determining the actu al clock period of the ulp oscillator: table 9-2. start-up times for the calibrated fa st rc oscillator clock selection sut2:0 start-up time from power-save additional delay from reset, typical values (2) 000 6 ck 14 ck + 4 ms 001 6 ck 14 ck + 8 ms 010 6 ck 14 ck + 16 ms 011 6 ck 14 ck + 32 ms 100 6 ck 14 ck + 64 ms 101 6 ck 14 ck + 128 ms 110 6 ck 14 ck + 256 ms 111 (1) 6 ck 14 ck + 512 ms slow rc period slow rc word - slow rc temp prediction word ( tt hot ) ? 64 --------------------------- ? 1024 ------------------------------------------------------------------------------------------------------------------------------- ----------------------------- = 28 8042a?avr?07/09 atmega16hvb/32hvb 1. to determine the accurate clock period as a function of die temperature, if needed by the application, the oscillator sampling interface should be used. refer to section ?osi ? oscillator sampling inte rface? on page 29 for details. 2. to determine a fixed value for the actual clock period independent of the die temperature, for example to determine the best setting of the battery protection timing, use the calibra- tion byte ulp_rc_frq stored in the signature address space, refer to section ?reading the signature row from software? on page 199 for details. 9.3 clock startup sequence when the cpu wakes up from powe r-save, the cpu clock source is used to time the start-up, ensuring a stable clock before instruction execution starts. when the cpu starts from reset, there is an additional delay allowing the voltage regulator to reach a stable level before com- mencing normal operation. the ultra low power rc oscillator is used for timing this real-time part of the start-up time. start-up times are determined by the sut fuses as shown in table 9-2 on page 27 . the number of ultra low power rc oscillator cycles used for each time-out is shown in table 9-3 . note: 1. the actual value depends on the actual clock period of the ultra low power rc oscillator, refer to ?ultra low power rc oscillator? on page 27 for details. 9.4 clock output the cpu clock divided by 2 can be output to the pb1 pin. the cpu can enable the clock output function by setting the ckoe bi t in the mcu control register. the clock will not run in any sleep modes. 9.5 system clock prescaler the atmega16hvb/32hvb has a system clock prescaler, used to prescale the calibrated fast rc oscillator. the system clock can be divided by setting the ?clkpr ? clock prescale regis- ter? on page 32 , and this enables the user to decrease or increase the system clock frequency as the requirement for power consumption and processing power changes. this system clock will affect the clock frequency of the cp u and all synchronous peripherals. clk i/o , clk cpu and clk- flash are divided by a factor as shown in table 9-4 on page 33 . when switching between prescaler settings, the system clock prescaler ensures that no glitches occurs in the clock system. it also ensures that no intermediate frequency is higher than table 9-3. number of ultra low po wer rc oscillator cycles typ time-out (1) number of cycles 4 ms 512 8 ms 1k 16 ms 2k 32 ms 4k 64 ms 8k 128 ms 16k 256 ms 32k 512 ms 64k 29 8042a?avr?07/09 atmega16hvb/32hvb neither the clock frequency corresponding to the previous setting, nor the clock frequency corre- sponding to the new setting. the ripple counter that implements the prescaler runs at the frequency of the undivided clock, and may be faster than the cpu's clock frequency. it is not possible to determine the state of the prescaler, and the exact time it takes to switch from one clock division to the other cannot be exactly predicted. from the time the clkps values are written, it takes between t1 + t2 and t1 + 2*t2 before the new clock frequency is active. in this interval, two active clock edges are pro- duced. here, t1 is the previous clock period, and t2 is the period corresponding to the new prescaler setting. to avoid unintentional changes of clock frequency, a special write procedure must be followed to change the clkps bits: 1. write the clock prescaler change enable (clkpce) bit to one and all other bits in clkpr to zero. 2. within four cycles, write the desired va lue to clkps while writing a zero to clkpce. interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. 9.6 vadc clock prescaler the vadc clock will be automatically prescaled rela tive to the system clock prescaler settings, see ?system clock prescaler? on page 28 . depending on the clock prescale select bits, clkps1..0, the vadc clock, clk vadc , will be prescaled by 8, 4, 2 or 1 as shown in table 9-5 on page 33 . 9.7 osi ? oscillator sampling interface 9.7.1 features ? runtime selectable oscillator input (slow rc or ulp rc oscillator) ? 7 bit prescaling of th e selected oscillator ? software read access to the ph ase of the prescaled clock ? input capture trigger so urce for timer/counter0 9.7.2 overview the oscillator sampling interfac e (osi) enables sampling of th e slow rc and ultra low power rc (ulp) oscillators in atmega 16hvb/32hvb. osi can be used to calibrate the fast rc oscil- lator runtime with high accuracy. osi can also provide an accurate reference for compensating the ulp oscillator frequency drift. this is useful for modules with high-precision requirements, such as the coulomb counter. the prescaled oscillator phase ca n be continuously read by th e cpu through the osicsr regis- ter. in addition, the input capture function of timer/counter0 can be set up to trigger on the rising edge of the prescaled clock. this enables accura te measurements of the oscillator frequencies relative to the fast rc oscillator. a simplified block diagram of the oscilla tor sampling interface is shown in figure 9-2 on page 30 . 30 8042a?avr?07/09 atmega16hvb/32hvb figure 9-2. oscillator sampling in terface block diagram the osi_posedge signal pulses on each rising edge of the prescaled clock. this signal is not directly accessible by the cpu, but can be us ed to trigger the input capture function of timer/counter0. using osi in combination with the input capture function of timer/counter0 facilitates accurate measurement of the oscillator frequencies with a minimum of cpu calcula- tion. refer to ?timer/counter (t/c0,t/c1)? on page 82 for details on how to enable the input capture function. osi_posedge databus ultra low power rc oscillator slow rc oscillator oscillator select 7 bit prescaler edge detector osisel0 osicsr fast rc oscillator 31 8042a?avr?07/09 atmega16hvb/32hvb 9.7.3 usage the slow rc oscillator repr esents a highly pr edictable and accurate cloc k source over the entire temperature range an d provides an excellent reference fo r calibrating the fast rc oscillator run- time. typically, runtime calibration is needed to provide an accurate fast rc frequency for asynchronous serial communication in the complete temperature range. the slow rc frequency at 85 c and the slow rc temperature coefficient are stored in the sig- nature row. these characteristics can be used to calculate the actual slow rc clock period at a given temperature with high precision. refer to ?slow rc oscillator? on page 27 for details. by measuring the number of cpu cycles of one or more prescaled slow rc clock periods, the actual fast rc oscillator cloc k period can be determin ed. the fast rc clo ck period can then be adjusted by writing to the fosccal register. t he new fast rc clock period after calibration should be verified by repeating the measurement and repeating the calibration if necessary. the fast rc clock period as a function of the slow rc clock period is given by: where n is the number of prescaled slow rc periods that is used in the measurement. using more prescaled slow rc periods decreases the measurement error, but increases the time con- sumed for calibration. note that the slow rc osc illator needs very short ti me to stabilize after being enabled by the osi module. hence, the calibration algorithm may use the time between the first and second osi_posedge as time reference for calculations. another usage of osi is determining the ulp frequency accurately. the ulp frequency at 85 c and the ulp temperature coefficient are stored in the signature row, allowing the ulp frequency to be calculated directly. however, the ulp frequency is less predictable over temperature than the slow rc oscillator frequency, t herefore a more accura te result can be ob tained by calculat- ing the ratio between the slow rc and ulp oscill ators. this is done by sampling both the ulp and slow rc oscillators and compar ing the results. when the ratio is known, the actual ulp fre- quency can be determined with high accuracy. the ulp rc clock period as a function of the slow rc clock peri od is given by: where n is the number of prescaled ulp rc and slow rc periods that is used in the measure- ment. using more prescaled ulp rc and slow rc periods decreases the measurement error, but increases the time consumed for calibration . note that the fosccal register must be kept at a constant value during this operation to ensure accurate results. these clock period calculations should be performed again when there is a significant change in die temperature since the previous calculation. the die temperature can be found using the volt- age adc, refer to section ?voltage adc ? 7-channel general purpose 12-bit sigma-delta adc? on page 117 for details. t fastrc t slowrc 128 n ? number of cpu cycles in n prescaled slow rc periods ------------------------------------------------------------------------------------------------------------------------------- ----------------- - ? = t ulprc t slowrc number of cpu cycles in n prescaled ulp rc periods number of cpu cycles in n prescaled slow rc periods ------------------------------------------------------------------------------------------------------------------------------- ----------------- - ? = 32 8042a?avr?07/09 atmega16hvb/32hvb 9.8 register description 9.8.1 fosccal ? fast rc oscillator calibration register ? bits 7:0 ? fcal7:0: fast rc oscillator calibration value the fast rc oscillator calibration register is used to trim the fast rc os cillator to remove pro- cess variations from the oscillator frequency. the factory-calibrated value is automatically written to this register during chip reset, giving an oscillator frequency of approximately 8.0 mhz at 25c. the application software can write this register to change the oscillato r frequency. the oscillator can be run-time calibra ted to any frequency in the range 7.3 - 8.1 mhz. calibration out- side that range is not guaranteed. note that this o scillator is used to time eeprom and flash write accesses , and these write times will be affected accordingly. if the eeprom or flash are writ ten, do not calibrate to more than 8.1 mhz. other wise, the eeprom or flash write may fail. the fcal[7:5] bits determine the range of operation for the oscillator. setting these bits to 0b000 gives the lowest frequency range, setting this bit to 0b111 gives the highest frequency range. the frequency ranges are overlapping. a setting of for instance fosccal = 0x1f gives a higher frequency than fosccal = 0x20. the fcal[4:0] bits are used to tune the frequency within the selected range. a setting of 0x00 gives the lowest frequency in that range, and a setting of 0x1f gives the highest frequency in the range. incrementing fcal[4:0] by 1 will give a fr equency increment of less than 1% in the fre- quency range 7.3 - 8.1 mhz. with an accurate time reference, an oscillator accuracy of 0.5% can be achieved after calibration. the frequency will drift with temperature, so run-time calibra- tion will be required to main tain the accuracy. refer to ?osi ? oscillator sampling interface? on page 29 for details. 9.8.2 mcucr ? mcu control register ? bit 5 ? ckoe: clock output when this bit is written to one, the cpu cl ock divided by 2 is output on the pb1 pin. 9.8.3 clkpr ? clock prescale register bit 76543210 (0x66) fcal7 fcal6 fcal5 fcal4 fcal3 fcal2 fcal1 fcal0 fosccal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value device spec ific calibration value bit 7 6 5 4 3 2 1 0 0x35 (0x55) -? ? ckoe pud ? ? ivsel ivce mcucr read/write r r r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 65432 1 0 (0x61) clkpce ? ? ? ? ? clkps1 clkps0 clkpr read/writer/w rrrrrr/wr/w initial value 0 00000 1 1 33 8042a?avr?07/09 atmega16hvb/32hvb ? bit 7 ? clkpce: clock prescaler change enable the clkpce bit must be written to logic one to enab le change of the clkps bits. the clkpce bit is only updated when the other bits in cl kpr are simultaneously wr itten to zero. clkpce is cleared by hardware four cycles af ter it is written or when clkps bits are written. rewriting the clkpce bit within this time-out period does neither extend the time-out period, or clear the clk- pce bit. ? bit 1:0 ? clkps1:0: clock prescaler select bit 1..0 these bits define the division factor between the selected clock source and the internal system clock. these bits can be written run-time to vary the clock frequency to suit the application requirements. as the divider divides the master clock input to the mcu, the speed of all synchro- nous peripherals is reduced when a division fact or is used. the division factors are given in table 9-4 on page 33 . note that writing to the system clo ck prescaler select bits will abort any ongoing vadc conversion. note: 1. when changing prescaler value, the vadc prescaler will automatically change frequency of the vadc clock and abort any ongoing conversion. 9.8.4 osicsr ? oscillator sampling interface control and status register ? bits 7:5,3:2 ? res: reserved bits these bits are reserved bits in the atme ga16hvb/32hvb and will always read as zero. table 9-4. system clock prescaler select clkps1 clkps0 clock division factor 001 012 104 118 table 9-5. vadc clock prescaling (1) clkps1 clkps0 vadc division factor 008 014 102 111 bit 7 6 5 4 3 2 1 0 0x17 (0x37) ? ? ? osisel0 ? ? osist osien osicsr read/write r r r r/w r r r r/w initial value 0 0 0 0 0 0 0 0 34 8042a?avr?07/09 atmega16hvb/32hvb ? bit 4 - osisel0: oscillator sampling interface select 0 ? bit 1 ? osist: oscillator sampling interface status this bit continuously displays the phase of the prescaled clock. this bit can be polled by the cpu to determine the rising and falling edges of the prescaled clock. ? bit 0 ? osien: oscillator sampling interface enable setting this bit enables the oscilla tor sampling interface. when this bit is cleared, the oscillator sampling interface is disabled. notes: 1. the prescaler is reset each time the osicsr register is written, and hence each time a new oscillator sour ce is selected. 2. enabling the osi module and selecting slow rc oscillator as input source is the only way to enable the slow rc oscillator. the slow rc oscillator will not run in any other modes. table 9-6. osisel bit description osisel0 oscillator source 0 ulp oscillator 1 slow rc oscillator 35 8042a?avr?07/09 atmega16hvb/32hvb 10. power management and sleep modes sleep modes enable the application to shut down unused modules in the mcu, thereby saving power. the avr provides various sleep modes allowing the user to tailor the power consump- tion to the application?s requirements. 10.1 sleep modes figure 9-1 on page 25 presents the different clock systems in the atmega16hvb/32hvb, and their distribution. the figure is helpful in selecting an appropriate sleep mode. the different sleep modes and their wake up sources is summarized in table 10-1 , and figure 10-1 on page 36 shows a sleep mode state diagram. notes: 1. discharge fet must be switched off for charge detect to be active. 2. when waking from power-off the charger detect will generate a power-on reset (por). from other sleep modes a charger detect interrupt will wake-up chip. to enter any of the sleep modes, the se bit in smcr, see ?smcr ? sleep mode control regis- ter? on page 39 , must be written to logic one and a sleep instruction must be executed. the sm2..0 bits in the smcr register select which sleep mode will be activated by the sleep instruction. see table 10-3 on page 40 for a summary. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu wakes up. the mcu is then halted for four cycles in addition to the st art-up time, executes the interrupt routine, and resumes execution from the instruction following sleep. the contents of the register file and sram are unaltered when the device wakes up from any sleep mode except power-off. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. table 10-1. wake-up sources for sleep modes mode wake-up sources bandgap buffer short circuit detection wake-up on regular current battery protection interrupts external interrupts wdt spm/eeprom ready cc-adc v-adc other i/o charger detect (1)(2) smbus address match and bus connect/disconnect voltage regulator warning idle x x x xxxxxxx x x adc noise reduction xxxxxxxx xxx power-save xxxxx x xx power-off x 36 8042a?avr?07/09 atmega16hvb/32hvb figure 10-1. sleep mode state diagram . reset active power-off power-save interrupt sleep reset from all states except power-on reset reset time-out sleep or black-out detection charger connected idle interrupt sleep black-out detection black-out detection adc nrm black-out detection sleep interrupt table 10-2. active modules in different sleep modes module mode active idle adc noise reduction power-save power-off rcosc_fast x x x x rcosc_ulp x x x x rcosc_slow x (1) x (1) osi x x cpu x flash x 8-bit timer/16-bit timer x x twi/smbus x x x (2) x (2) spi x x v-adc x x x cc-adc x x x x 37 8042a?avr?07/09 atmega16hvb/32hvb notes: 1. runs only when osi is enabled and rcosc_slow is selected as source for osi. 2. address match and bus connect/disconnect wake-up only 3. discharge fet must be switched off for charger detect to be enabled. 4. vregmon interrupt (regulator operation condition warning) not available. 10.2 idle mode when the sm2..0 bits are written to 000, the sleep instruction makes the mcu enter idle mode, stopping the cpu but allowing all peripheral functions to continue operating. this sleep mode basically halts clk cpu and clk flash , while allowing the other clocks to run. idle mode enables the mcu to wake up from external triggered interrupts as well as internal ones like the timer overflow interrupt. 10.3 adc noise reduction when the sm2:0 bits are written to 001, the sleep instruction makes the mcu enter adc noise reduction mode, stopping the cpu but a llowing the voltage adc (v-adc), voltage reg- ulator monitor (vregmon), watchdog timer (wdt), coulomb counter (cc), current battery protection (cbp), and the ultr a low power rc oscillator (rcosc _ulp) to continue operating. this sleep mode basically halts clk i/o , clk cpu , and clk flash , while allowing the other clocks to run. this improves the noise environment for the voltage adc, enabling higher accuracy on measurements. 10.4 power-save mode when the sm2..0 bits are written to 011, the sleep instruction makes the mcu enter power- save mode. in this mode, the internal fast rc oscillator (rcosc_fast) is stopped, while watchdog timer (wdt), coulomb counter (cc), current battery protection (cbp) and the ultra low power rc oscillator (rco sc_ulp) continue operating. this mode will be the default mode when application software doe s not require operation of cpu, flash or any of the periphe ral units running at the fast in ternal oscillato r (rcosc_fast). if the current through the sense resistor is so small that the coulomb counter cannot measure it accurately, regular current detection should be enabled to reduce power consumption. the wdt keeps accurately track of the time so that battery self discharge can be calculated. external interrupts x x x x battery protection x x x x watchdog timer x x x x voltage regulator x x x x (4) bandgap reference x x x x fet driver x x x x charger_detect (3) xxxxx table 10-2. active modules in different sleep modes (continued) module mode active idle adc noise reduction power-save power-off 38 8042a?avr?07/09 atmega16hvb/32hvb note that if a level triggered interrupt is used for wake-up from power-save mode, the changed level must be held for some time to wake up the mcu. refer to ?external interrupts? on page 58 for details. when waking up from power-save mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. this allows the clock to restart and become stable after having been stopped. the wake-up period is defined in ?clock sources? on page 26 . 10.5 power-off mode when the sm2..0 bits are written to 100 and the se bit is set, the sleep instruction makes the cpu shut down the voltage regulator, leaving on ly the charger detect circuitry operational. to ensure that the mcu enters po wer-off mode only when intende d, the sleep instruction must be executed within 4 clock cycles a fter the sm2..0 bits are written. the mcu will reset when return- ing from power-off mode. note: before entering power-off sleep mode, interrupts should be disabled by software. otherwise inter- rupts may prevent the sleep instruction fr om being executed within the time limit. 10.6 power reduction register the power reduction register (prr), see ?prr0 ? power reduction register 0? on page 40 , provides a method to stop the clock to individual peripherals to reduce power consumption. the current state of the peripheral is frozen and the i/o registers can not be read or written. resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled be fore stopping the clock. waking up a module, which is done by clearing the bit in prr, puts the module in the same state as before shutdown. module shutdown can be used in idle mode and ac tive mode to significantly reduce the overall power consumption. in all other sleep modes, the clock is already stopped. 10.7 minimizing power consumption there are several issues to consider when trying to minimize the power consumption in an avr controlled system. in general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possi ble of the device?s functions are operating. all functions not needed should be disabled. in particular, the following modules may need special consideration when trying to achieve th e lowest possible power consumption. 10.7.1 watchdog timer if the watchdog timer is not needed in the application, the module should be turned off. if the watchdog timer is enabled, it will be enabled in all sleep modes except power-off. the watch- dog timer current consumption is signific ant only in power-save mode. refer to ?watchdog timer? on page 46 for details on how to configure the watchdog timer. 10.7.2 port pins when entering a sleep mode, all port pins should be configured to use minimum power. the most important is then to ensure that no pins drive resistive loads. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buffers of the device will be disabled. this ensures that no power is consumed by the input logic when not needed. in some cases, the input logic is needed for detec ting wake-up conditions, and it will then be enabled. refer to the section ?digital input enable and sleep modes? on page 71 for details on which pins are enabled. if the input buffer is enabl ed and the input signal is left floating or have an analog signal level close to v reg /2, the input buffer will use excessive power. 39 8042a?avr?07/09 atmega16hvb/32hvb for analog input pins, the digital input buffer should be disabled at all times. an analog signal level close to v reg /2 on an input pin can cause significant current even in active mode. digital input buffers can be disabled by writing to the digital input disable register. refer to ?didr0 ? digital input disable register 0? on page 122 for details. 10.7.3 on-chip debug system a programmed dwen fuse enable s some parts of the clock system to be running in all sleep modes. this will increase the power consumption while in sleep. thus, the dwen fuse should be disabled when debugwire is not used. 10.7.4 battery protection if one of the battery protection features is not needed by the application, this feature should be disabled, see ?bpcr ? battery protection control register? on page 141. the current consump- tion in the battery protection circuitry is on ly significant in power-s ave mode. disabling both fets will automatically disable th e battery protec tion module in order to save power. the band- gap reference should always be enabled whenever battery protection is enabled. 10.7.5 voltage adc if enabled, the v-adc will consume power independent of sleep mode. to sa ve power, the v- adc should be disabled when not used, and before entering power-save sleep mode. see ?voltage adc ? 7-channel general purpose 12-bit sigma-delta adc? on page 117 for details on v-adc operation. 10.7.6 coulomb counter if enabled, the cc-adc will consume power inde pendent of sleep mode. to save power, the cc-adc should be disabled when not used, or set in regular current detection mode. see ?coulomb counter - dedicated fuel gauging sigma-delta adc? on page 108 for details on cc- adc operation. 10.7.7 bandgap voltage reference if enabled, the bandgap reference will consume power independent of sleep mode. to save power, the bandgap reference should be disabled when not used as reference for the voltage adc, the coloumb counter or battery protection. see ?voltage reference and temperature sensor? on page 123 for details. 10.8 register description 10.8.1 smcr ? sleep m ode control register the sleep mode control register contains control bits for power management. ? bits 7:4 ? res: reserved bits these bits are reserved bits in the atmega 16hvb/32hvb, and will always read as zero. ? bits 3:1 ? sm2:0: sleep mode select bits 2, 1 and 0 bit 76543210 0x33 (0x53) ? ? ? ? sm2 sm1 sm0 se smcr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 40 8042a?avr?07/09 atmega16hvb/32hvb these bits select between the four available sleep modes as shown in table 10-3 . ? bit 0 ? se: sleep enable the se bit must be written to logic one to make the mcu enter the sleep mode when the sleep instruction is executed. to avoid the mcu enteri ng the sleep mode unless it is the programmer?s purpose, it is recommended to write the sleep enable (se) bit to one just before the execution of the sleep instruction and to clear it immediately af ter waking up. 10.8.2 prr0 ? power reduction register 0 ? bit 7, 4 - res: reserved bits these bits are reserved for future use. for com patibility with future devices, these bits must be written to zero when prr0 is written. ? bit 6 - prtwi: power reduction twi writing a logic one to this bit shuts down the twi by stopping the clock to the module. when waking up the twi again, the twi should be re initialized to ensure proper operation. ? bit 5 - prvrm: power reduction voltage regulator monitor writing a logic one to this bit shuts down the voltage regulator monitor interface by stopping the clock of the module. ? bit 3 - prspi: power reduction serial peripheral interface writing logic one to this bit shuts down the seri al peripheral interface by stopping the clock to the module. when waking up the spi again, the spi should be reinitialized to ensure proper operation. ? bit 2 - prtim1: power reduction timer/counter1 writing a logic one to this bit shuts down the timer/counter1 module. when the timer/counter1 is enabled, operation will cont inue like before the shutdown. table 10-3. sleep mode select sm2 sm1 sm0 sleep mode 000idle 0 0 1 adc noise reduction 010reserved 011power-save 100power-off 101reserved 110reserved 111reserved bit 7 6 5 4 3 2 1 0 (0x64) ? prtwi prvrm ? prspi prtim1 prtim0 prvadc prr0 read/write r r/w r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 41 8042a?avr?07/09 atmega16hvb/32hvb ? bit 1 - prtim0: power reduction timer/counter0 writing a logic one to this bit shuts down the timer/counter0 module. when the timer/counter0 is enabled, operation will cont inue like before the shutdown. ? bit 0 - prvadc: power reduction v-adc writing a logic one to this bit shuts down the v-adc. before wr iting the prvadc bit, make sure that the vaden bit is cleared to minimize the power consumption. note: v-adc control registers can be up dated even if the prvadc bit is set. 42 8042a?avr?07/09 atmega16hvb/32hvb 11. system control and reset 11.1 resetting the avr during reset, all i/o registers are set to their initial values, and the program starts execution from the reset vector. the instruction placed at the reset vector must be a jmp ? absolute jump ? instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. the circuit diagram in ?reset logic? on page 43 shows the reset logic. table 12-1 on page 52 defines the electrical parameters of the reset circuitry. the i/o ports of the avr are immediately reset to their initial state when a reset source goes active. this does not require any clock source to be running. after all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. this allows the voltage regulator to reach a stable level before normal operation starts. the time-out period of the delay counter is defined by the user through the sut fuses. the dif- ferent selections for the delay period are presented in ?clock sources? on page 26 . 11.2 reset sources the atmega16hvb/32hvb has five sources of reset: ? the power-on reset module generates a power-on reset when the voltage regulator starts up. ? external reset. the mcu is rese t when a low level is present on the reset pin for longer than the minimum pulse length. ? watchdog reset. the mcu is reset when the watchdog timer period expires and the watchdog is enabled. ? brown-out reset. the mcu is reset when v reg is below the brown-out reset threshold, v bot . see ?brown-out detection? on page 45. ? debugwire reset. in on-chip debug mode, the debugwire resets the mcu when giving the reset command. 43 8042a?avr?07/09 atmega16hvb/32hvb figure 11-1. reset logic 11.2.1 power-on reset and charger connect the voltage regulator will not star t up until the charger detect module has enabl ed it. before this happens the chip will be in power-off mode and only the charger detect module is enabled. in order for the charger detect module to enable the voltage regulator, the voltage at the batt pin must exceed the power-on threshold voltage, v pot . when the voltage at the batt pin exceeds v pot , the voltage regulator starts up and the chip enters reset mode. when the delay counter times out, the ch ip will enter active mode. see figure 10-1 on page 36 . for details on charger detect, see ?charger detect? on page 129 . mcu status register (mcusr) reset circuit delay counters ck timeout wdrf extrf porf data b u s clock generator spike filter pull-up resistor bodrf ultra low power rc oscillator sut[1:0] power-on reset circuit/ charger detect watchdog timer reset /dw v fet batt por v reg counter reset brown-out detection v reg debugwire ocdrf 44 8042a?avr?07/09 atmega16hvb/32hvb figure 11-2. powering up atmega16hvb/32hvb 11.2.2 external reset an external reset is generated by a low level on the reset pin. reset pulses longer than the minimum pulse width (see table 32-3 on page 230 ) will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay counter starts the mcu after the time-out period ? t tout ? has expired. figure 11-3. external reset during operation 11.2.3 watchdog reset when the watchdog times out, it will generate a short reset pulse of one ck cycle duration. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . refer to page 46 for details on operation of the watchdog timer. power-off sleep_mode por v batt internal_reset t tout reset active v pot v reg 3.3 v 45 8042a?avr?07/09 atmega16hvb/32hvb figure 11-4. watchdog reset during operation 11.2.4 brown-out detection atmega16hvb/32hvb has an on-chip brown-out detection (bod) circuit for monitoring the v cc level during operation by comparing it to a fixed trigger level v bot . the trigger level has a hysteresis to ensure spike free brown-out dete ction. the hysteresis on the detection level should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot - v hyst /2. the bod is automatically enab led in all modes of operation, except in power-off mode. when the bod is enabled, and v cc decreases to a value below the trigger level (v bot- in figure 11-5 ), the brown-out reset is immediately activated. when v cc increases above the trigger level (v bot+ in figure 11-5 ), the delay counter starts the mcu after the time-out period t tout has expired. figure 11-5. brown-out reset during operation 11.3 reset and the voltage reference the voltage reference is import ant for the performance of the s ystem as the vref voltage will be used as reference voltage for several modules. it is therefore important to notice that after a reset condition the voltage reference needs calibration and settling before the vref voltage is accurate. for details on voltage reference calibration and settling time, see ?voltage reference and temperature sensor? on page 123 . ck fet v cc reset time-out internal reset v bot- v bot+ t tout 46 8042a?avr?07/09 atmega16hvb/32hvb 11.4 watchdog timer 11.4.1 features ? clocked from separat e on-chip oscillator ? 3 operating modes ?interrupt ? system reset ? interrupt and system reset ? selectable time-out period from 16 ms to 8s ? possible hardware fuse watchdog al ways on (wdton) for fail-safe mode 11.4.2 overview atmega16hvb/32hvb has an enhanced watchdog timer (wdt). the wdt counts cycles of the ultra low power rc oscillator. the wdt give s an interrupt or a system reset when the counter reaches a given time-out value. in normal operation mode, it is required that the system uses the wdr - watchdog timer reset - instruction to restart the counter before the time-out value is reached. if the system doesn't restart the counter, an interrupt or system reset will be issued. figure 11-6. watchdog timer in interrupt mode, the wdt gives an interrupt when the timer expires. this interrupt can be used to wake the device from sleep-modes, and also as a general system timer. one example is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected. in system reset mode, the wdt gives a reset when the timer expires. this is typically used to prevent sys tem hang-up in case of runaway code. the third mode, interrupt and system reset mode, combines the other two modes by first giving an inter- rupt and then switch to system reset mode. this mode will for instance allow a safe shutdown by saving critical parameters before a system reset. the watchdog always on (wdton ) fuse, if programmed, will forc e the watchdog timer to sys- tem reset mode. with the fuse programmed the system reset mode bit (wde) and interrupt mode bit (wdie) are locked to 1 and 0 respectively. to further ensure program security, altera- tions to the watchdog set-up must follow timed sequences. the sequence for clearing wde and changing time-out configuration is as follows: ultra low power rc oscillator 16 ms 32 ms 64 ms 0.13s 0.26s 0.51s 1.0s 2.0s 4.1s 8.2s wdp0 wdp1 wdp2 wdp3 watchdog reset wde wdif wdie mcu reset interrupt 47 8042a?avr?07/09 atmega16hvb/32hvb 1. in the same operation, write a logic one to the watchdog change enable bit (wdce) and wde. a logic one must be written to wde regardless of the previous value of the wde bit. 2. within the next four clock cycles, write the wde and watchdog prescaler bits (wdp) as desired, but with the wdce bit cleared. this must be done in one operation. the following code example shows one assembly and one c function for turning off the watch- dog timer. the example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during th e execution of these functions. note: 1. see ?about code examples? on page 8. assembly code example (1) wdt_off: ; turn off global interrupt cli ; reset watchdog timer wdr ; clear wdrf in mcusr in r16, mcusr andi r16, (0xff & (0< 50 8042a?avr?07/09 atmega16hvb/32hvb ? bit 6 - wdie: watchdog interrupt enable when this bit is written to one and the i-bit in t he status register is set, the watchdog interrupt is enabled. if wde is cleared in combination with this setting, the watchdog timer is in interrupt mode, and the corresponding interrupt is executed if time-out in the watchdog timer occurs. if wde is set, the watchdog timer is in interrupt and system reset mode. the first time-out in the watchdog timer will set wdif. executing t he corresponding interrup t vector will clear wdie and wdif automatically by hardware (the watchd og goes to system reset mode). this is use- ful for keeping the watchdog timer security while using the interrupt. to stay in interrupt and system reset mode, wdie must be set after each interrupt. this should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the watchdog system reset mode. if the interrupt is not executed before the next time-out, a sys- tem reset will be applied. note: 1. wdton fuse set to ?0? means programmed, ?1? means unprogrammed. ? bit 5, 2:0 - wdp3:0 : watchdog timer prescaler 3, 2, 1 and 0 the wdp3..0 bits determine the watchdog timer prescaling when the watchdog timer is enabled. the different prescaling values and their corresponding timeout periods are shown in table 11-2 . ? bit 4 - wdce: watchdog change enable this bit is used in timed sequences for changi ng wde and prescaler bits. to clear the wde bit, and/or change the prescaler bits, wdce must be set. once written to one, ha rdware will clear wdce after four clock cycles. ? bit 3 - wde: watchdog system reset enable wde is overridden by wdrf in mcusr. this m eans that wde is always set when wdrf is set. to clear wde, wdrf must be cleared first. this feature ensures multiple resets during con- ditions causing failure, and a safe start-up after the failure. ? bits 5, 2:0 ? wdp3:0: watchdog timer prescaler 3, 2, 1, and 0 the wdp3..0 bits determine the watchdog timer prescaling when the watchdog timer is enabled. the different prescaling values and their corresponding timeout periods are shown in table 11-2 on page 51 . table 11-1. watchdog timer configuration wdton (1) wde wdie mode action on time-out 1 0 0 stopped none 1 0 1 interrupt mode interrupt 1 1 0 system reset mode reset 111 interrupt and system reset mode interrupt, then go to system reset mode 0 x x system reset mode reset 51 8042a?avr?07/09 atmega16hvb/32hvb . note: 1. the actual timeout value depends on the actual clock period of the ultra low power rc oscil- lator, refer to ?ultra low power rc oscillator? on page 27 ? for details. table 11-2. watchdog timer prescale select wdp3 wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out (1) 0 0 0 0 2k cycles 16 ms 0 0 0 1 4k cycles 32 ms 0 0 1 0 8k cycles 64 ms 0 0 1 1 16k cycles 0.13s 0 1 0 0 32k cycles 0.26s 0 1 0 1 64k cycles 0.51s 0 1 1 0 128k cycles 1.0s 0 1 1 1 256k cycles 2.0s 1 0 0 0 512k cycles 4.1s 1 0 0 1 1024k cycles 8.2s 1010 reserved 1011 1100 1101 1110 1111 52 8042a?avr?07/09 atmega16hvb/32hvb 12. interrupts 12.1 overview this section describes the specifics of the interrupt handling as performed in atmega16hvb/32hvb. for a general explanation of the avr interrupt handling, refer to ?reset and interrupt handling? on page 14 . 12.2 interrupt vectors in atmega16hvb/32hvb . table 12-1. reset and interrupt vectors vector no. program address (1) source interrupt definition 1 0x0000 reset external pin, power-on reset, brown-out reset, watchdog reset, and debugwire reset 2 0x0002 bpint battery protection interrupt 3 0x0004 vregmon voltage regulator monitor interrupt 4 0x0006 int0 external interrupt request 0 5 0x0008 int1 external interrupt request 1 6 0x000a int2 external interrupt request 2 7 0x000c int3 external interrupt request 3 8 0x000e pcint0 pin change interrupt 0 9 0x0010 pcint1 pin change interrupt 1 10 0x0012 wdt watchdog time-out interrupt 11 0x0014 bgscd bandgap buffer short circuit detected 12 0x0016 chdet charger detect 13 0x0018 timer1 ic timer/counter 1 input capture 14 0x001a timer1 compa timer/c ounter 1 compare match a 15 0x001c timer1 compb timer/c ounter 1 compare match b 16 0x001e timer1 ovf timer/counter 1 overflow 17 0x0020 timer0 ic timer/counter 0 input capture 18 0x0022 timer0 compa timer/c ounter 0 compare match a 19 0x0024 timer0 compb timer /counter0 compare match b 20 0x0026 timer0 ovf timer/counter 0 overflow 21 0x0028 twi bus c/d two-wire bus connect/disconnect 22 0x002a twi two-wire serial interface 23 0x002c spi, stc spi, serial transfer complete 24 0x002e vadc voltage adc conversion complete 25 0x0030 ccadc conv cc-adc instantaneous current conversion complete 26 0x0032 ccadc reg cur cc-adc regular current 53 8042a?avr?07/09 atmega16hvb/32hvb notes: 1. when the ivsel bit in mcucr is set, interrup t vectors will be moved to the start of the boot flash section. the address of each interrupt vector will then be the address in this table added to the start address of the boot flash section. 2. when the bootrst fuses are pr ogrammed, the device will jump to the boot loader address at reset, see ?boot loader support ? read-while-write self-programming? on page 191 . if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. table 12-2 shows reset and interrupt vectors plac ement for the various combinations of bootrst and ivsel settings. if the program never enables an in terrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. note: 1. the boot reset address is shown in table 29-5 on page 204 . for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. the most typical and general program setup for the reset and interrupt vector addresses in atmega16hvb/32hvb is: 27 0x0034 ccadc acc cc-adc accumulate current conversion complete 28 0x0036 ee ready eeprom ready 29 0x0038 spm spm ready table 12-2. reset and interrupt vectors placement (1) bootrst ivsel reset address interru pt vectors start address 1 0 0x0000 0x0002 1 1 0x0000 boot reset address + 0x0002 0 0 boot reset address 0x0002 0 1 boot reset address boot reset address + 0x0002 table 12-1. reset and interrupt vectors (continued) vector no. program address (1) source interrupt definition address labels code comments 0x0000 jmp reset ; reset handler 0x0002 jmp bpint ; battery protection interrupt handler 0x0004 jmp vregmon_int ; voltage regulator monitor interrupt handler 0x0006 jmp ext_int0 ; external interrupt request 0 handler 0x0008 jmp ext_int1 ; external interrupt request 1 handler 0x000a jmp ext_int2 ; external interrupt request 2 handler 0x000c jmp ext_int3 ; external interrupt request 3 handler 0x000e jmp pcint0 ; pin change interrupt 0 handler 0x0010 jmp pcint1 ; pin change interrupt 1 handler 0x0012 jmp wdt ; watchdog time-out interrupt 0x0014 jmp bgscd ; bandgap buffer short circuit detected 0x0016 jmp chdet ; charger detect 0x0018 jmp tim1_ic ; timer1 input capture handler 0x001a jmp tim1_compa ; timer1 compare a handler 54 8042a?avr?07/09 atmega16hvb/32hvb when the bootrst fuse is unprogrammed , the boot section size set to 4k by tes and the ivsel bit in the mcucr reg- ister is set before any interrupts are enabled, the most typical and general program setup for the reset and interrupt vector addresses is: address labels code comments 0x0000 reset: ldi r16,high(ramend); main program start 0x0001 out sph,r16 ; set stack pointer to top of ram 0x0002 ldi r16,low(ramend) 0x0003 out spl,r16 0x0004 sei ; enable interrupts 0x0005 55 8042a?avr?07/09 atmega16hvb/32hvb ... ... ... ; 0x002c jmp spm_rdy ; store program memory ready handler ; .org 0x4c00 0x4c00 reset: ldi r16,high(ramend); main program start 0x4c01 out sph,r16 ; set stack pointer to top of ram 0x4c02 ldi r16,low(ramend) 0x4c03 out spl,r16 0x4c04 sei ; enable interrupts 0x4c05 56 8042a?avr?07/09 atmega16hvb/32hvb 12.3 moving interrupts between application and boot space the general interrupt control register controls the placement of the interrupt vector table. 12.4 register description 12.4.1 mcucr ? mcu control register ? bit 1 ? ivsel: interrupt vector select when the ivsel bit is cleared (z ero), the interrupt vectors are pl aced at the star t of the flash memory. when this bit is set (one), the interrupt vectors are moved to the beginning of the boot loader section of the flash. the actual address of the start of the boot flash section is deter- mined by the bootsz fuses. refer to the section ?boot loader support ? read-while-write self-programming? on page 191 for details. to avoid unintentional changes of interrupt vector tables, a special write procedure must be followed to change the ivsel bit: a. write the interrupt vector change enable (ivce) bit to one. b. within four cycles, write the desired valu e to ivsel while writing a zero to ivce. interrupts will automatically be di sabled while this sequence is executed. interrupts are disabled in the cycle ivce is set, and they remain disabl ed until after the instru ction following the write to assembly code example move_interrupts: ; enable change of interrupt vectors ldi r16, (1< 58 8042a?avr?07/09 atmega16hvb/32hvb 13. external interrupts 13.1 overview the external interrupts are triggered by the int3:0 pin or any of the pcint11:0 pins. observe that, if enabled, the interrupts w ill trigger even if the int3:0 or pcint11:0 pins are configured as outputs. this feature provides a way of generating a software interrupt. the external interrupts can be triggered by a falli ng or rising edge or a low level. this is set up as indicated in the specification for the ?eicra ? external interrupt control register a? on page 58 . when the external interrupt is enabled and is configured as level tr iggered, the interrupt will trigger as long as the pin is held low. interrupts are detected asynchronously. this implies that these interrupts can be used for waking the part also from sleep modes other than idle mode. the i/o clock is halted in all sleep modes except idle mode. the pin change inte rrupt pci1 will trigger if any enabl ed pcint11:4 pin toggles and pin change interrupts pci0 will trigger if any enabled pcin t3:0 pin toggles. pcmsk1 and pcmsk0 regis- ters control which pins contribute to the pin change interrupts. pin change interrupts on pcint11:0 are detected asynchronously. this implies that these interrupts can be used for wak- ing the part also from sleep modes other than idle mode. note that if a level triggered interrupt is used for wake-up from power-save, the required level must be held long enough for the mcu to complete the wake-up to trigger the level interrupt. if the level disappears before the end of the start-up ti me, the mcu will still wake up, but no inter- rupt will be generated. the star t-up time is defined by the sut fuses as described in ?clock systems and their distribution? on page 25 . 13.2 register description 13.2.1 eicra ? external interrupt control register a ? bits 7:0 ? iscn: external interrupt sense control bits the external interrupts 3:0 are activated by the external pins int3:0 if the sreg i-flag and the corresponding interrupt mask in the eimsk is set. the level and edges on the external pins that activate the interrupts are defined in table 13-1 on page 59 . edges on int3..int0 are registered asynchronously. pulses on int3:0 pins wi der than the minimum pulse width given in table 32- 11 on page 233 will generate an interrupt. shorter pulses are not guaranteed to generate an interrupt. if low level interrupt is selected, the low level must be held until the completion of the currently executing instru ction to generate an interrupt. if e nabled, a level trig gered inte rrupt will generate an interrupt request as long as the pi n is held low. when changing the iscn bit, an interrupt can occur. therefore, it is recommended to first disable intn by clearing its interrupt enable bit in the eimsk register. then, the iscn bit can be changed. finally, the intn interrupt flag should be cleared by writing a logical one to its interrupt flag bit (intfn) in the eifr regis- ter before the interrupt is re-enabled. bit 76543210 (0x69) isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 eicra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 59 8042a?avr?07/09 atmega16hvb/32hvb note: 1. n = 3, 2, 1, or 0. when changing the iscn1/iscn0 bits, the interrupt must be disabled by clearing its interrupt enable bit in the eimsk register. otherwise an interrupt can occur when the bits are changed. 13.2.2 eimsk ? external interrupt mask register ? bits 7:4 ? res: reserved bits these bits are reserved bits ins the atm ega16hvb/32hvb, and will always read as zero. ? bits 3:0 ? int3 - int0: external interrupt request 3:0 enable when an int3 ? int0 bit is written to one and the i-bit in the status register (sreg) is set (one), the corresponding external pin interrupt is enabled. the interrupt sense control bits in the external interrupt control register ? eicra ? defines whether the external interrupt is activated on rising or falling edge or level sensed. activi ty on any of these pins will trigger an interrupt request even if the pin is enabled as an output. this provides a way of generating a software interrupt. 13.2.3 eifr ? external interrupt flag register ? bits 7:4 ? res: reserved bits these bits are reserved bits ins the atm ega16hvb/32hvb, and will always read as zero. ? bits 3:0 ? intf3 - intf0: external interrupt flags 3:0 when an edge or logic change on the int3:0 pin triggers an interrupt request, intf3:0 becomes set (one). if the i-bit in sreg and the corresponding interrupt enable bit, int3:0 in eimsk, are set (one), the mcu will jump to the interrupt vector . the flag is cleared wh en the interr upt routine is executed. alternatively, the flag can be cleared by writing a logical one to it. these flags are always cleared when int3:0 are configured as level interrupt. note that when entering sleep mode with the int3:0 inte rrupts disabled, the input buffers on these pins will be disabled. this may cause a logic change in internal si gnals which will set the intf3:0 flags. see ?digital input enable and sleep modes? on page 71 for more information. table 13-1. interrupt sense control iscn1 iscn0 description 0 0 the low level of intn generates an interrupt request. 0 1 any logical change on intn generates an interrupt request. 1 0 the falling edge of intn generates an interrupt request. 1 1 the rising edge of intn generates an interrupt request. bit 76543210 0x1d (0x3d) ? ? ? ? int3 int2 int1 int0 eimsk read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x1c (0x3c) ? ? ? ? intf3 intf2 intf1 intf0 eifr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 60 8042a?avr?07/09 atmega16hvb/32hvb 13.2.4 pcicr ? pin change interrupt control register ? bits 7:2 ? res: reserved bits these bits are reserved bits ins the atm ega16hvb/32hvb, and will always read as zero. ? bit 1 ? pcie1: pin change interrupt enable 1 when the pcie1 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 1 is enabled. any change on any enabled pcin t11..4 pin will cause an inter- rupt. the corresponding interrupt of pin change interrupt request is executed from the pci1 interrupt vector. pcint11..4 pins are enabled individually by the pcmsk1 register. ? bit 0 ? pcie0: pin change interrupt enable 0 when the pcie0 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 0 is enabled. any change on any enabled pcint3..0 pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci0 interrupt vector. pcint3..0 pins are enabled individually by the pcmsk0 register. 13.2.5 pcifr ? pin change interrupt flag register ? bits 7:2 ? res: reserved bits these bits are reserved bits ins the atm ega16hvb/32hvb, and will always read as zero. ? bit 1 ? pcif1: pin change interrupt flag 1 when a logic change on any pcint11..4 pin triggers an interrupt request, pcif1 becomes set (one). if the i-bit in sreg and the pcie1 bit in eimsk are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alter- natively, the flag can be cleared by writing a logical one to it. ? bit 0 ? pcif0: pin change interrupt flag 0 when a logic change on any pcint3:0 pin triggers an interrupt request, pcif0 becomes set (one). if the i-bit in sreg and the pcie0 bit in eimsk are set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is executed. alter- natively, the flag can be cleared by writing a logical one to it. 13.2.6 pcmsk1 ? pin change mask register 1 bit 76543210 (0x68) ------pcie1pcie0pcicr read/write rrrrrrr/wr/w initial value00000000 bit 76543210 0x1b (0x3b) ------pcif1pcif0pcifr read/write rrrrrrr/wr/w initial value00000000 bit 76543210 (0x6c) pcint11 pcint10 pcint9 pcint8 pcint7 pcint6 pcint5 pcint4 pcmsk1 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 61 8042a?avr?07/09 atmega16hvb/32hvb ? bit 7:0 ? pcint11:4: pin change enable mask 15..8 these bits select whether pin change interrupt is enabled on the corresponding i/o pin. if pcint11:4 is set and the pcie1 bit in eimsk is set, pin change interrupt is enabled on the cor- responding i/o pin. if pcint11:4 is cleared, pi n change interrupt on the corresponding i/o pin is disabled. 13.2.7 pcmsk0 ? pin change mask register 0 ? bits 7:4 ? res: reserved bits these bits are reserved bits ins the atm ega16hvb/32hvb, and will always read as zero. ? bit 3:0 ? pcint3:0: pin change enable mask 3:0 each pcint3:0 bit selects whether pin change interrupt is enabled on the corresponding i/o pin. if pcint3:0 is set and the pcie0 bit in pcicr is set, pin change interrupt is enabled on the cor- responding i/o pin. if pcint3:0 is cleared, pi n change interrupt on the corresponding i/o pin is disabled. bit 76543210 (0x6b) - - - - pcint3 pcint2 pcint1 pcint0 pcmsk0 read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 62 8042a?avr?07/09 atmega16hvb/32hvb 14. high voltage i/o ports 14.1 overview all high voltage avr ports have true read-modify-write functionality when used as general dig- ital i/o ports. this means that the state of one port pin can be changed without unintentionally changing the state of any other pin with the sbi and cbi instructions. all high voltage i/o pins have protection zener diodes to ground as indicated in figure 14-1 . see ?electrical characteris- tics? on page 228 for a complete list of parameters. figure 14-1. high voltage i/o pin equivalent schematic all registers and bit references in this section are written in general form. a lower case ?x? repre- sents the numbering letter for the port, and a lower case ?n? represents the bit number. however, when using the register or bit defines in a progr am, the precise form must be used. for example, portc3 for bit number three in port c, here documented generally as portxn. the physical i/o registers and bit locations are listed in ?register description? on page 66 . one i/o memory address location is allocated for each high voltage port, the data register ? portx. the data register is read/write. using the i/o port as general digital output is described in ?high voltage ports as general dig- ital i/o? on page 63 . c pin logic see figure "general high voltage digital i/o" for details pxn 63 8042a?avr?07/09 atmega16hvb/32hvb 14.2 high voltage ports as general digital i/o the high voltage ports are high voltage tolerant open collector output ports. in addition they can be used as general digital inputs. figure 14-2 shows a functional description of one output port pin, here generically called pxn. figure 14-2. general high voltage digital i/o (1) notes: 1. wrx, rrx and rpx are common to all pins within the same port. clk i/o and sleep are com- mon to all ports. 2. the high voltage digital i nput is not present on pc5. 14.2.1 configuring the pin each port pin consist of two register bits: portxn and pinxn. as shown in ?register descrip- tion? on page 66 , the portxn bits are accesed at the portx i/o address, and the pinxn bits at the pinx i/o address. if portxn is written logic one, the port pin is dr iven low (zero). if portxn is written logic zero, the port pin is tri-stated. the port pins are tri-stated when a reset condition becomes active, even if no clocks are running. 14.2.2 reading the pin the port pin can be read through the pinxn register bit. as shown in figure 14-2 , the pinxn register bit and the preceding latch constitute a synchronizer. this is needed to avoid metasta- bility if the physical pin changes value near the edge of the internal clock, bu t it also introduces a delay. wrx sleep: sleep control clki/o: i/o clock sleep pxn q d q portxn _ clr data b u s rrx synchronizer q d clr pinxn clk i/o q _ d l q q set clr _ reset rpx rrx: read portx register wrx: write portx register rpx: read pinx register high voltage digital input (2) 64 8042a?avr?07/09 atmega16hvb/32hvb 14.3 overview 14.4 alternate port functions the high voltage i/o has alternate port functi ons in addition to being general digital i/o. figure 14-3 shows how the port pin control signals from the simplified figure 14-2 on page 63 can be overridden by alternate functions. figure 14-3. high voltage digital i/o (1)(2) notes: 1. wrx, rrx and rpx are common to all pins within the same port. clk i/o and sleep are com- mon to all ports. all other signals are unique for each pin. 2. the high voltage digital i nput is not present on pc5. table 14-1 on page 65 summarizes the function of the overriding signals. the pin and port indexes from figure 14-3 are not shown in the succeeding t ables. the overriding signals are generated internally in the modules having the alternate function. wrx pvovxn pvoexn pvoexn: pxn port value override enable pvovxn: pxn port value override value dieoexn: pxn digital input-enable override enable dieovxn: pxn digital input-enable override value sleep pxn dieoexn dieovxn q d q portxn _ clr 1 0 1 0 databus rrx synchronizer q d clr pinxn clk i/o q _ d l q q set clr _ reset rpx dixn rrx: read portx register wrx: write portx register rpx: read pinx register clk i/o : i/o clock dixn: digital input pin n on portx sleep: sleep control 65 8042a?avr?07/09 atmega16hvb/32hvb 14.4.1 alternate functions of port c the port c pins with alternate functions are shown in table 14-2 . the alternate pin configuration is as follows: ? int0/ extprot - port c, bit 0 int0: external interrupt source 0. this pin can serve as external interrupt source. int0 can be used as an interrupt pin regardless of whether another function is enabled or not. extprot: external battery protection input. this pin can serve as external battery protection input to be able to override the fet controller externally. ? int1 - port c, bit1 int1: external interrupt source 1. this pin can serve as external interrupt source. int1 can be used as an interrupt pin regardless of whether another function is enabled or not. ? int2 - port c, bit2 int2: external interrupt source 2. this pin can serve as external interrupt source. int2 can be used as an interrupt pin regardless of whether another function is enabled or not. table 14-1. generic description of overriding signals for alternate functions signal name full name description pvoe port value override enable if this signal is set and the ou tput driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. dieoe digital input enable override enable if this bit is set, the digital input enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital input is enabled/disabled when dieov is set/cleared, regardless of the mcu state (normal mode, sleep mode). di digital input this is the digital input to alte rnate functions. in the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. table 14-2. port c pins alternate functions port pin alternate function pc0 int0/ extprot(external interrupt 0 or external battery protection input) pc1 int1 (external interrupt 1) pc2 int1 (external interrupt 2) pc3 int3/ sda (external interrupt 3 or sm bus data line) pc4 scl (sm bus clock line) 66 8042a?avr?07/09 atmega16hvb/32hvb ? int3/ sda - port c, bit3 int3: external interrupt source 3. this pin can serve as external interrupt source. int3 can be used as an interrupt pin regardless of whether another function is enabled or not. sda: sm bus data. this pin can serve as bidirectional serial data line for the 2-wire serial interface. ? scl - port c, bit4 scl: sm bus clock. this pin can serve as bidirectional clock line for the 2-wire serial interface table 14-3 on page 66 relates the alternate functions of port c to the overriding signals shown in figure 14-3 on page 64 . 14.5 register description 14.5.1 portc ? port c data register 14.5.2 pinc ? port c input pins address table 14-3. overriding signals for alternate functions in pc4:0 signal name pc4/scl pc3/int3/sda pc2/in t2 pc1/int1 pc0/int0/extprot pvoe sm bus enabled sm bus enabled extprot enable pvov sm bus clock sm bus data 1 dieoe sm bus enabled int3 enable sm bus enabled int2 enable int1enable int0 enable extprot enable dieov 1 1 1 1 1 di sm bus clock int3 input sm bus data int2 input int1 input int0 input extprot input didr bit 76543210 0x08 (0x28) ? ? portc5 portc4 portc3 portc2 portc1 portc0 portc read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x06 (0x26) ?? - pinc4 pinc3 pinc2 pinc1 pinc0 pinc read/writerrrrrrrr initial value n/a n/a n/a n/a n/a n/a n/a n/a 67 8042a?avr?07/09 atmega16hvb/32hvb 15. low voltage i/o-ports 15.1 overview all low voltage avr ports have tr ue read-modify-write functionality when used as general digi- tal i/o ports. this means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with th e sbi and cbi instructio ns. the same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). all low voltage port pins hav e individually selectable pull-up resistors with a supply-voltage invariant resistance. all i/o pins have protection diodes to both v reg and ground as indicated in figure 15-1 . refer to ?electrical characteristics? on page 228 for a complete list of parameters. figure 15-1. low voltage i/o pin equivalent schematic all registers and bit references in this section are written in general form. a lower case ?x? repre- sents the numbering letter for the port, and a lower case ?n? represents the bit number. however, when using the register or bit defines in a progr am, the precise form must be used. for example, portb3 for bit no. 3 in port b, here documented generally as portxn. the physical i/o regis- ters and bit locations are listed in ?register description? on page 78 . three i/o memory address locations are allocated for each low voltage port, one each for the data register ? portx, data direction register ? ddrx, and th e port input pins ? pinx. the port input pins i/o location is read only, while the data register and the data direction register are read/write. however, writing a logic one to a bi t in the pinx register, will result in a toggle in the corresponding bit in the data register. in addition, the pull-up disable ? pud bit in mcucr disables the pull-up function for all low voltage pins in all ports when set. using the i/o port as general digital i/o is described in ?low voltage ports as general digital i/o? on page 68 . many low voltage port pins are multiplexed with alternate functions for the peripheral features on the device. how each alternate function interferes with the port pin is described in ?alternate port functions? on page 72 . refer to the individual module sections for a full description of the alternate functions. c pin logic r pu see figure "general digital i/o" for details pxn 68 8042a?avr?07/09 atmega16hvb/32hvb note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital i/o. 15.2 low voltage ports as general digital i/o the low voltage ports are bi-directional i/o ports with optional internal pull-ups. figure 15-2 shows a functional description of one i/o-port pin, here generically called pxn. figure 15-2. general low voltage digital i/o (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. 15.2.1 configuring the pin each port pin consists of three register bits: ddxn, portxn, and pinxn. as shown in ?register description? on page 78 , the ddxn bits are accessed at the ddrx i/o address, the portxn bits at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects the direct ion of this pin. if ddxn is written logic one, pxn is configured as an output pin. if ddxn is written logic zero, pxn is configured as an input pin. if portxn is written logic one when the pin is c onfigured as an input pin, the pull-up resistor is activated. to switch the pull-up resistor off, portxn has to be written logic zero or the pin has to be configured as an output pin. the port pins are tri-stated when reset condition becomes active, even if no clocks are running. clk rpx rrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data b u s sleep sleep: sleep control pxn i/o wpx 0 1 wrx wpx: write pinx register 69 8042a?avr?07/09 atmega16hvb/32hvb if portxn is written logic one when the pin is conf igured as an output pin, the port pin is driven high (one). if portxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 15.2.2 toggling the pin writing a logic one to pinxn toggles the value of portxn, independent on the value of ddrxn. note that the sbi instruction can be used to toggle one single bit in a port. 15.2.3 switching between input and output when switching between tri-state ({ddxn, portxn} = 0b00) and output high ({ddxn, portxn} = 0b11), an intermediate state with either pull-up enabled {ddxn, portxn} = 0b01) or output low ({ddxn, portxn} = 0b10) must occur. norma lly, the pull-up enabled state is fully accept- able, as a high-impedant enviro nment will not notice the differenc e between a strong high driver and a pull-up. if this is not the case, the pud bit in the mcucr register can be set to disable all pull-ups in all ports. switching between input with pull-up and output low generates the same problem. the user must use either the tri-state ({ddxn, portxn} = 0b00) or the output high state ({ddxn, portxn} = 0b11) as an intermediate step. table 15-1 summarizes the control signals for the pin value. 15.2.4 reading the pin value independent of the setting of data direction bit ddxn, the port pin can be read through the pinxn register bit. as shown in figure 15-2 , the pinxn register bit and the preceding latch con- stitute a synchronizer. this is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. figure 15-3 shows a timing dia- gram of the synchronization when reading an externally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. table 15-1. port pin configurations ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input no tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pulled low. 0 1 1 input no tri-state (hi-z) 1 0 x output no output low (sink) 1 1 x output no output high (source) 70 8042a?avr?07/09 atmega16hvb/32hvb figure 15-3. synchronization when reading an externally applied pin value consider the clock period starting shortly after the first falling edge of the system cl ock. the latch is closed when the clock is low, and goes transpa rent when the clock is high, as indicated by the shaded region of the ?sync latch? signal. the signal value is latched when the system clock goes low. it is clocked into the pinxn register at the succeeding positive clock edge. as indi- cated by the two arrows tpd,max and tpd,min, a single signal tr ansition on the pin will be delayed between ? and 1? system clock period depending upon the time of assertion. when reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in figure 15-4 . the out instruction sets the ?sync latch? signal at the positive edge of the clock. in this case, the delay tpd through the synchronizer is 1 system clock period. figure 15-4. synchronization when reading a software assigned pin value the following code example shows how to set port b pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. the resulting pin values are read back again, but as previously di scussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. xxx in r17, pinx 0x00 0xff instructions sync latch pinxn r17 xxx system clk t pd, max t pd, min out portx, r16 nop in r17, pinx 0xff 0x00 0xff system clk r16 instructions sync latch pinxn r17 t pd 71 8042a?avr?07/09 atmega16hvb/32hvb note: 1. for the assembly program, two temporary registers are used to minimize the time from pull- ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. 15.2.5 digital input enable and sleep modes as shown in figure 15-2 on page 68 , the digital input signal can be clamped to ground at the input of the schmischmidtt-trigge r. the signal denoted sleep in the figure, is set by the mcu sleep controller in power-save mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to v reg /2. sleep is overridden for port pins enabled as ex ternal interrupt pins. if the external interrupt request is not e nabled, sleep is active also for these pins. sl eep is also overri dden by various other alternate functions as described in ?alternate port functions? on page 72 . if a logic high level (?one?) is present on an asynchronous external interrupt pin configured as ?interrupt on rising edge, falling edge, or any logic change on pin? while the external interrupt is not enabled, the corresponding external interrupt flag will be set when resuming from the above mentioned sleep mode, as the clamping in these sleep mode produces the requested logic change. assembly code example (1) ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16,(1< 73 8042a?avr?07/09 atmega16hvb/32hvb note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. all other signals are unique for each pin. table 15-2 summarizes the function of the overriding signals. the pin and port indexes from fig- ure 15-5 on page 72 are not shown in the succeeding tables. the overriding signals are generated internally in the modules having the alternate function. the following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. refer to the alternate function description for further details. table 15-2. generic description of overriding signals for alternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when {ddxn, portxn, pud} = 0b010. puov pull-up override value if puoe is set, the pull-up is enabled/disabled when puov is set/cleared, regardless of the setting of the ddxn, portxn, and pud register bits. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cleared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output driver is enabled/disabled when ddov is set/cleared, regardless of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the ou tput driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital i nput enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital input is enabled/disabled when dieov is set/cleared, regardless of the mcu state (normal mode, sleep mode). di digital input this is the digital input to alte rnate functions. in the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. aio analog input/output this is the analog input/output to/from alternate functions. the signal is connected directly to the pad, and can be used bi- directionally. 74 8042a?avr?07/09 atmega16hvb/32hvb 15.3.1 alternate functions of port a the port a pins with alternate functions are shown in table 15-3 . the alternate pin configuration is as follows: ? adc0/sgnd/pcint0 - port a, bit0 adc0: voltage adc channel0. this pin can serve as channel 0 input for the voltage adc. sgnd: voltage adc signal ground. this pin can serve as channel 1 signal ground for the voltage adc. pcint0. pin change interrupt 0. this pin can serve as external interrupt source. ? adc1/sgnd/pcint1 - port a, bit1 adc1: voltage adc channel 1: this pin can serve as channel 1 for the voltage adc. sgnd: voltage adc signal ground. this pin can serve as channel 0 signal ground for the voltage adc. pcint1: pin change interrupt 1. this pin can serve as external interrupt source. ? t0/pcint2 - port a, bit2 t0: timer/counter0. this pin can serve as timer/counter0 clock source. pcint2: pin change interrupt 2. this pin can serve as external interrupt source. ? t1/pcint3 - port a, bit3 t1: timer/counter1. this pin can serve as timer/counter1 clock source. pcint3: pin change interrupt 3. table 15-3. port a pins alternate functions port pin alternate function pa3 t1/pcint3 (timer/counter1 clock input or pin change interrupt 3) pa2 t0/pcint2 (timer/counter0 clock input or pin change interrupt 2) pa 1 adc1/sgnd/pcint1 (adc input channel 1, signal ground or pin change interrupt 1) pa 0 adc0/sgnd/pcint0 (adc input channel 0, signal ground or pin change interrupt 0) 75 8042a?avr?07/09 atmega16hvb/32hvb these pins can serve as external interrupt source table 15-4 relates the alternate functions of port a to the overriding signals shown in figure 15-5 on page 72 . 15.3.2 alternate functions of port b the port b pins with alternate functions are shown in table 15-5 . the alternate pin configuration is as follows: ? miso/pcint11 - port b, bit7 miso, master data input: slave data output pin for spi channel. when the spi is enabled as a master, this pin is configured as an input r egardless of the setting of ddb7. when the spi is enabled as a slave, the data direction of this pi n is controlled by ddb7. when the pin is forced by the spi to be an input, the pu ll-up can still be controlled by t he portb7 bit. wh en not operat- ing in spi mode, this pin can serve as an external interrupt source. pcint11: pin change interrupt 11. this pi n can serve as external interrupt source. table 15-4. overriding signals for alternate functions in pa3:pa0 signal name pa3/t1/pcint3 pa2/t0/pcint2 pa 1/adc1/sgnd/pcint1 pa0/adc0/sgnd/pcint0 puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 vadsc ? vadmux=adc0 vadsc ? vadmux=adc1 ddov 0 0 1 1 pvoe 0 0 vadsc ? vadmux=adc0 vadsc ? vadmux=adc1 pvov 0 0 0 0 ptoe - - - - dieoe pcint3 ? pcie0 pcint2 ? pcie0 didr1| (pcint1 ? pcie0) didr0 | (pcint0 ? pcie0) dieov 1 1 didr1 didr0 di t1 input pcint3 input t0 input pcint2 input pcint1 input pcint0 input aio - - adc1 input/ sgnd adc0 input/ sgnd table 15-5. port b pins alternate functions port pin alternate functions pb7 miso/pcint11 (spi bus master input/ slave output or pin change interrupt 11) pb6 mosi/pcint10 (spi bus master outpu t/slave input or pin change interrupt 10) pb5 sck/pcint9 (spi bus serial clock or pin change interrupt 9) pb4 ss /pcint8 (spi bus slave select input or pin change interrupt 8) pb3 pcint7 (pin change interrupt 7) pb2 pcint6 (pin change interrupt 6) pb1 ckout/pcint5 (clock output or pin change interrupt 5) pb0 pcint4/icp00 (pin change interrupt 4 or timer/counter0 input capture trigger ) 76 8042a?avr?07/09 atmega16hvb/32hvb ? mosi/pcint10 - port b, bit6 mosi, spi master data output: slave data input for spi channel. when the spi is enabled as a slave, this pin is configured as an input r egardless of the setting of ddb6. when the spi is enabled as a master, the data direction of this pi n is controlled by ddb6. when the pin is forced by the spi to be an input, the pu ll-up can still be controlled by t he portb6 bit. wh en not operat- ing in spi mode, this pin can serve as an external interrupt source. pcint10: pin change interrupt 10. this pi n can serve as external interrupt source. ? sck/pcint9 - port b, bit5 sck, master clock output: slave clock input pin for spi channel. when the spi is enabled as a slave, this pin is configured as an input r egardless of the setting of ddb5. when the spi is enabled as a master, the data direction of this pi n is controlled by ddb5. when the pin is forced by the spi to be an input, the pull-up can still be controlled by the portb5 bit. pcint9: pin change interrupt 9. this pin can serve as external interrupt source. ?ss /pcint8 - port b, bit4 ss, slave select input: when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb4. as a slave, the spi is activated when this pin is driven low. when the spi is enabled as a master, the data di rection of this pin is controlled by ddb4. when the pin is forced by the spi to be an input, the pull-up can still be controlled by the portb4 bit. when not operating in spi mode, this pin can serve as clock output, cpu clock divided by 2. see ?clock output? on page 28. pcint8: pin change interrupt 8. this pin can serve as external interrupt source. ? pcint7 - port b, bit3 pcint7: pin change interrupt 7. this pin can serve as external interrupt source. ? pcint6 - port b, bit2 pcint6: pin change interrupt 6. this pin can serve as external interrupt source. ? ckout/pcint5 - port b, bit1 ckout: clock output. this pin ca n serve as clock output pin. pcint5: pin change interrupt 5. this pin can serve as external interrupt source. ? icp00/pcint4 - port b, bit0 icp00: input capture timer/counter0. this pin can serve as input capture trigger for timer/counter0 pcint4: pin change interrupt 4. this pin can serve as external interrupt source. 77 8042a?avr?07/09 atmega16hvb/32hvb table 15-6. overriding signals for alternate functions in pb7:pb4 signal name pb7/miso/pcint11 pb6/ mosi/pcint10 pb5/sck/pcint9 pb4/ss/ pcint8 puoe spe ? mstr spe ? mstr spe ? mstr spe ? mstr puov portb7 ? pud portb6 ? pud portb5 ? pud portb0 ? pud ddoe spe ? mstr spe ? mstr spe ? mstr spe ? mstr ddov 0 0 0 0 pvoe spe ? mstr spe ? mstr spe ? mstr 0 pvov spi slave output spi mstr output sck output 0 ptoe ? ? ? ? dieoe pcint11 ? pcie1 pcint10 ? pc ie1 pcint9 ? pcie1 pcint8 ? pcie1 dieov 1 1 ? 1 di spi mstr input pcint11 input spi slave input pcint10 input sck input pcint9 input ss input pcint8 input aio ? ? ? ? table 15-7. overriding signals for alternate functions in pb3:pb0 signal name pb3/pcint7 pb2/pcin t6 pb1/ckoe/pcint5 pb0/pcint4 puoe 0 0 ckoe 0 puov 0 0 0 0 ddoe 0 0 ckoe 0 ddov 0 0 ckoe 0 pvoe 0 0 ckoe 0 pvov 0 0 ckout 0 ptoe ? ? ? ? dieoe pcint7 ? pcie1 pcint6 ? pcie1 (pc int6 ? pcie1)|ckoe pcint4 ? pcie1 dieov 1 1 (pcint6 ? pcie1)|ckoe 1 di pcint7 input pcint6 input pcint5 input ipc0 input pcint4 input aio ? ? ? ? 78 8042a?avr?07/09 atmega16hvb/32hvb 15.4 register description 15.4.1 mcucr ? mcu control register ? bit 4 ? pud: pull-up disable when this bit is written to one, the pull-ups in the i/o ports are disabled even if the ddxn and portxn registers are configured to enable the pull-ups ({ddxn, portxn} = 0b01). see ?con- figuring the pin? on page 68 for more details about this feature. 15.4.2 porta ? port a data register 15.4.3 ddra ? port a data direction register 15.4.4 pina ? port a input pins address 15.4.5 portb ? port b data register 15.4.6 ddrb ? port b data direction register 15.4.7 pinb ? port b input pins address bit 7 6 5 4 3 2 1 0 0x35 (0x55) ? ? ckoe pud ? ? ivsel ivce mcucr read/write r r r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x02 (0x22) - - - - porta3 porta2 porta1 porta0 porta read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x01 (0x21) ---- dda3 dda2 dda1 dda0 ddra read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x00 (0x20) ---- pina3 pina2 pina1 pina0 pina read/write r r r r r/w r/w r/w r/w initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 0x05 (0x25) portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x04 (0x24) ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x03 (0x23) pinb7 pinb6 pinb5 pinb4 pi nb3 pinb2 pinb1 pinb0 pinb read/writerrrrrrrr initial value n/a n/a n/a n/a n/a n/a n/a n/a 79 8042a?avr?07/09 atmega16hvb/32hvb 16. timer/counter0 and ti mer/counter1 prescalers 16.1 overview timer/counter1 and timer/counter0 share the same prescaler module, but the timer/counters can have different prescaler settings. the description below applies to both timer/counter1 and timer/counter0. 16.1.1 internal clock source the timer/counter can be clocked directly by the system clock (by setting the csn2:0 = 1). this provides the fastest operation, with a maximum timer/counter clock frequency equal to system clock frequency (f clk_i/o ). alternatively, one of four taps from the prescaler can be used as a clock source. the prescaled clock has a frequency of either f clk_i/o /8, f clk_i/o /64, f clk_i/o /256, or f clk_i/o /1024. 16.1.2 prescaler reset the prescaler is free running, i.e., operates independently of the clock select logic of the timer/counter, and it is shared by timer/counter1 and timer/counter0. since the prescaler is not affected by the timer/counter? s clock select, the state of t he prescaler will have implications for situations where a prescaled clock is used. one example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > csn2:0 > 1). the number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to n+1 system clock cycles, where n equals the prescaler divisor (8, 64, 256, or 1024). it is possible to use the prescaler reset for synchronizing the timer/counter to program execu- tion. however, care must be taken if the other timer/counter that shares the same prescaler also uses prescaling. a prescaler reset will affect the prescaler period for all timer/coun ters it is connected to. figure 16-1. prescaler for timer/counter psrsync clear clk tn tn clk i/o synchronization csn0 csn1 csn2 n 80 8042a?avr?07/09 atmega16hvb/32hvb 16.2 external clock source an external clock source applied to the tn pin can be used as timer/counter clock (clk tn ). the tn pin is sampled once every system clock cycle by the pin synchronization logic. the synchro- nized (sampled) signal is then passed through the edge detector. figure 16-2 shows a functional equivalent block diagram of the tn synchroniza tion and edge detector logic. the registers are clocked at the positive edge of the internal system clock ( clk i/o ). the latch is transparent in the high period of the internal system clock. the edge detector generates one clk t n pulse for each positive (csn2:0 = 7) or negative (csn2:0 = 6) edge it detects. see table 16-1 on page 81 for details. figure 16-2. tn pin sampling the synchronization and e dge detector logic introduces a de lay of 2.5 to 3.5 system clock cycles from an edge has been applied to the tn pin to the counter is updated. enabling and disabling of the clock input must be done when tn has been stable for at least one system clock cycle, otherwise it is a risk that a false timer/counter clock pulse is generated. each half period of the external clock applie d must be longer than one system clock cycle to ensure correct sampling. the external clock must be guaranteed to have less than half the sys- tem clock frequency (f extclk < f clk_i/o /2) given a 50/50% duty cycle. since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling fre- quency (nyquist sampling theorem). however, due to variation of the system clock frequency and duty cycle caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than f clk_i/o /2.5. an external clock source can not be prescaled. note: the synchronization logic on the input pins ( tn) is shown in figure 16-2 . tn_sync (to clock select logic) edge detector synchronization dq dq le dq tn clk i/o 81 8042a?avr?07/09 atmega16hvb/32hvb 16.3 register description 16.3.1 tccrnb ? timer/coun ter n control register b ? bits 2, 1, 0 ? csn2, csn1, csn0: clock select0, bit 2, 1, and 0 the clock select n bits 2, 1, and 0 define the prescaling source of timer n. if external pin modes are used for the timer/count er n, transitions on the tn pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 16.3.2 general timer/counter control register ? gtccr ? bit 7 ? tsm: timer/counter synchronization mode writing the tsm bit to one activates the timer/counter synchronization mode. in this mode, the value that is written to the psrsync bit is kept, hence keeping the corresponding prescaler reset signals asserted. this ensures that the corresponding timer/counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. when the tsm bit is written to zero the psrsync bit is cleared by hardware, and the timer/counters start counting simultaneously. ? bit 0 ? psrsync: prescaler reset when this bit is one, timer/co unter1 and timer/counter 0 prescaler will be reset. this bit is nor- mally cleared immediately by hardware, except if the tsm bit is set. note that timer/counter1 and timer/counter0 share the same prescaler and a reset of this prescaler will affect both timers. bit 76543210 (0x80)(0x81) - - - - - csn2 csn1 csn0 tccrnb read/write r r r r r r/w r/w r/w initial value00000000 table 16-1. clock select bit description csn2 csn1 csn0 description 0 0 0 no clock source (timer/counter stopped) 001clk i/o /(no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on tn pin. clock on falling edge. 1 1 1 external clock source on tn pin. clock on rising edge. bit 7654321 0 0x23 (0x43) tsm ? ? ? ? ? ? psrsync gtccr read/writer/wrrrrrr r/w initial value0000000 0 82 8042a?avr?07/09 atmega16hvb/32hvb 17. timer/counter (t/c0,t/c1) 17.1 features ? clear timer on compar e match (auto reload) ? input capture unit ? four independent interrupt sources (tovn, ocfna, ocfnb, icfn) ? 8-bit mode with two independent output compare units ? 16-bit mode with one indepe ndent output compare unit 17.2 overview timer/counter n is a general purpose 8-/16-bi t timer/counter module, with two/one output compare units and input capture feature. atmega16hvb/32hvb has two timer/counters, timer/counter0 and timer/counter1. the functionality for both timer/counters is descr ibed below. timer/counter0 and timer/counter1 have different timer/counter registers, as shown in ?register summary? on page 254 . the timer/counter general operation is described in 8-/16-bit mode. a simplified block diagram of the 8-/16-bit timer/counter is shown in figure 17-1 . cpu accessible i/o registers, including i/o bits and i/o pins, are shown in bold. the de vice-specific i/o register and bit locations are listed in the ?register description? on page 94 . figure 17-1. 8-/16-bit timer/counter block diagram 17.2.1 registers the timer/counter low byte register (tcntnl) and output compare registers (ocrna and ocrnb) are 8-bit registers. interrupt request (abbreviated to int.req. in figure 17-1 on page 82 ) signals are all visible in the timer interrupt fl ag register (tifr). all interrupts are individually masked with the timer interrupt mask register (timsk). tifr and timsk are not shown in the figure. in 16-bit mode the timer/counter consists one more 8-bit register, the timer/counter high byte register (tcntnh). furthermore, there is only one output compare unit in 16-bit mode as the two output compare registers, ocrna and ocrnb, are combined to one 16-bit output com- pare register. ocrna contains the low byte of the word and ocrnb contains the higher byte of clock select timer/counter data b u s ocrnb = tcntnl noise canceler icpn0 = edge detector control logic top count clear direction tovn (int. req.) ocna (int. req.) ocnb (int. req.) icfn (int. req.) tccrna tccrnb tn edge detector ( from prescaler ) clk tn = ocrna tcntnh fixed top value icpn1 83 8042a?avr?07/09 atmega16hvb/32hvb the word. when accessing 16-bit registers, special procedures described in section ?accessing registers in 16-bit mode? on page 90 must be followed. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the tn pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk tn ). 17.2.2 definitions many register and bit references in this section are written in general form. a lower case ?n? replaces the module number, e.g. timer/counte r number. a lower case ?x? replaces the unit, e.g. ocrnx and icpnx describes ocrna/b and icp1/0x . however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt0l for accessing timer/counter0 counter value and so on. the definitions in table 17-1 are also used extensively throughout the document. 17.3 timer/counter clock sources the timer/counter can be clocked internally, via the prescaler, or by an external clock source. the clock select logic is controlled by the clock select (csn2:0) bits located in the timer/coun- ter control register n b (tccrnb), and controls which clock source and edge the timer/counter uses to increment its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk tn ). for details on clock source s and prescaler, see ?timer/counter0 and timer/counter1 prescalers? on page 79 17.4 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 17-2 on page 83 shows a block diagram of the counter and its surroundings. figure 17-2. counter unit block diagram table 17-1. definitions bottom the counter reaches the bottom when it becomes 0. max the counter reaches its maximum when it becomes 0xff (decimal 255) in 8-bit mode or 0xffff (decimal 65535) in 16-bit mode. top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff/0xffff (max) or the value stored in the ocrna register. data b u s tcntn control logic count tovn (int.req.) clock select top tn edge detector ( from prescaler ) clk tn 84 8042a?avr?07/09 atmega16hvb/32hvb signal description (internal signals): count increment or decrement tcntn by 1. clk t n timer/counter clock, referred to as clk tn in the following. top signalize that tcntn has reached maximum value. the counter is incremented at each timer clock (clk tn ) until it passes its top value and then restarts from bottom. the counting sequence is determined by the setting of the wgmn0 bits located in the timer/counter control regist er (tccrna). for more details about counting sequences, see ?timer/counter timing diagrams? on page 89 . clk tn can be generated from an external or internal clock source, selected by the clock select bits (csn2:0). when no clock source is selected (csn2:0 = 0) the timer is stopped. however, the tcntn value can be accessed by the cpu, regardless of whether clk tn is present or not. a cpu write overrides (has priority over) all counter clear or count operati ons. the timer/counter overflow flag (tovn) is set when the counter reaches the maximum value and it can be used for generating a cpu interrupt. 17.5 modes of operation the mode of operation is defined by the timer/counter width (tcwn), input capture enable (icenn) and the waveform generation mode (wgmn0)bits in ?tccrna ? timer/counter n control register a? on page 94 . table 17-2 on page 84 shows the different modes of operation. 17.5.1 normal 8-bit mode in the normal mode, the counter (tcntnl) is incr ementing until it overruns when it passes its maximum 8-bit value (max = 0xff) and then restarts from the bottom (0x00), see table 17-2 on page 84 for bit settings. the overflow flag (tovn) will be set in the same timer clock cycle as the tcntnl becomes zero. the tovn flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tovn flag, the timer resolution can be increased by software. there are no special cases to consider in the normal 8-bit mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. 17.5.2 clear timer on compare match (ctc) 8-bit mode in clear timer on compare or ctc mode, the ocrna register is used to manipulate the coun- ter resolution, see table 17-2 on page 84 for bit settings. in ctc mode the counter is cleared to table 17-2. modes of operation mode icenn tcwn wgmn0 timer/counter mode of operation top update of ocrx at tov flag set on 0 0 0 0 normal 8-bit mode 0xff immediate max (0xff) 1 0 0 1 8-bit ctc ocrna immediate max (0xff) 2 0 1 0 16-bit mode 0xffff immediate max (0xffff) 3 0 1 1 16-bit ctc ocrnb, ocrna immediate max (0xffff) 410 0 8-bit input capture mode 0xff ? max (0xff) 511 0 16-bit input capture mode 0xffff ? max (0xffff) 85 8042a?avr?07/09 atmega16hvb/32hvb zero when the counter value (tcntn) matches the ocrna. the ocrna defines the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies th e operation of counting external events. the timing diagram for the ctc mode is shown in figure 17-3 on page 85 . the counter value (tcntn) increases until a compare match occurs between tcntn and ocrna, and then coun- ter (tcntn) is cleared. figure 17-3. ctc mode, timing diagram an interrupt can be generated each time the counter value reaches the top value by using the ocfna flag. if the interrupt is enabled, the in terrupt handler routine can be used for updating the top value. however, changing top to a va lue close to bottom when the counter is run- ning with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocrna is lower than the current value of tcntn, the counter will miss the compar e match. the counter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. as for the normal mode of operation, the tovn flag is set in the same timer clock cycle that the counter counts from max to 0x00. 17.5.3 16-bit mode in 16-bit mode, the counter (tcntnh/l) is a incr ementing until it overruns when it passes its maximum 16-bit value (max = 0xffff) and then restarts from the bottom (0x0000), see table 17-2 on page 84 for bit settings. the overflow flag (t ovn) will be set in the same timer clock cycle as the tcntnh/l becomes zero. the tovn flag in this case behaves like a 17th bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tovn flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written any- time. the output compare unit can be used to generate interrupts at some given time. 17.5.4 clear timer on compare match (ctc) 16-bit mode in clear timer on compare 16-bit mode, ocrana/b registers are used to manipulate the coun- ter resolution, see table 17-2 on page 84 for bit settings. in ctc mode the counter is cleared to zero when the counter value (tcntn) matches ocrna/b, where ocrnb represents the eight most significant bits and ocrna represents the eight least significant bits. ocrna/b defines the top value of the counter, hence also its resolution. this mode allows greater control of the com- pare match output frequency. it also simplifies the operation of counting external events. an interrupt can be generated each time the counter reaches the top value by using the ocfna flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing the top to a value close the bottom when the counter is run- ning with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocrna/b is lower than the current tcntn ocnx interrupt flag set 1 4 period 2 3 86 8042a?avr?07/09 atmega16hvb/32hvb value of tcntn, the counter will miss the compar e match. the counter will then have to count to its maximum value (0xffff) and wrap around starting at 0x0000 before compare match can occur. as for the 16-bit mode, the tovn flag is set in the same timer clock cycle that the counter counts from max to 0x0000. 17.5.5 8-bit input capture mode the timer/counter can be used in a 8-bit input capture mode, see table 17-2 on page 84 for bit settings. for full description, see ?input capture unit? on page 86 . 17.5.6 16-bit input capture mode the timer/counter can also be used in a 16-bit input capture mode, see table 17-2 on page 84 for bit settings. for full description, see ?input capture unit? on page 86 . 17.6 input capture unit the timer/counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence . the external signal indicates an event, or mul- tiple events. for timer/counter0, the events can be applied via the pb0 pin (icp00), or alternatively via the osi_pose dge pin on the oscillator samp ling interface (icp01). for timer/counter1, the events can be applied by the battery protection interrupt (icp10) or alter- natively by the voltage regulator interrupt (icp11). the time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. alternatively the time- stamps can be used for creating a log of the events. the input capture unit is illustrate d by the block diagram shown in figure 17-4 on page 86 . the elements of the block diagram that are not directly a part of the input capture unit are gray shaded. figure 17-4. input capture unit block diagram the output compare register ocrna is a dual-purpose register that is also used as an 8-bit input capture register icrn. in 16-bit input capture mode the output compare register ocrnb serves as the high byte of the input capture register icrn. in 8-bit input capture mode the output compare register ocrnb is free to be used as a normal output compare register, icfn (int.req.) write icrn (16-bit register) ocrnb (8-bit) noise canceler icpn0 edge detector temp (8-bit) data bus (8-bit) ocrna (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) icncn icesn icpn1 icsn 87 8042a?avr?07/09 atmega16hvb/32hvb but in 16-bit input capture mode the output compare unit cannot be used as there are no free output compare register(s). even though the input capture register is called icrn in this sec- tion, it is referring to the output compare register(s). for more information on how to access the 16-bit registers refer to ?accessing registers in 16-bit mode? on page 90 . when a change of the logic level (an event) occurs on the input capture pin (icpx), and this change confirms to the setting of the edge detect or, a capture will be tr iggered. when a capture is triggered, the value of the counter (tcntn) is written to the i nput capture register (icrn). the input capture flag (icfn) is set at the same system clock as the tcntn value is copied into input capture register. if enabled (ticien=1), the input capture flag generates an input cap- ture interrupt. the icfn flag is automatically cleared when the interrupt is executed. alternatively the icfn flag can be cleared by software by writing a logical one to its i/o bit location. 17.6.1 input capture trigger source the default trigger source for the input capture unit is the i/o port pb0 in timer/counter0 and the battery protection interrupt in timer/counter1. alternatively can the osi_posedge pin on the oscillator sampling interface in timer/co unter0 and voltage regulator interrupt in timer/counter1 be used as trigger sources. the osi_posedge pin in timer/counter0 control register a (tccr0a) and the voltage regulator interrupt bit in the timer/counter1 control register a (tccr1a) is selected as trigger sources by setting the input capture select (ics0/1) bit. be aware that changing trigger source can trigger a capture. the input capture flag must therefore be cleared after the change. both input capture inputs are sampled using the same technique. the edge detector is also identical. however, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. an input capture on timer/counter0 can also be triggered by soft ware by controlling the port of the pb0 pin. 17.6.2 noise canceler the noise canceler improves noise immunity by using a simple digital filtering scheme. the noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the input capture noise canceler (icncn) bit in timer/counter control register n b (tccrnb) . when enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the icrn register. the noise canceler uses the system clock and is therefore not affected by the prescaler. 17.6.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured value in th e icrn register before the nex t event occurs, the icrn will be overwritten with a new value. in this case the result of the ca pture will be incorrect. when using the input capture interrupt, the icrn register should be read as early in the inter- rupt handler routine as possible. the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. measurement of an external signal duty cycle requires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as possible after the icrn register has been read. after a change of the edge, the input capture flag (icfn) must be 88 8042a?avr?07/09 atmega16hvb/32hvb cleared by software (writing a logical one to the i/o bit location). for measuring frequency only, the trigger edge change is not required. note: 1. see ?osi ? oscillator sampling interface? on page 29 for details. 2. the noise canceler cannot be used with this source. note: 1. the noise canceller will filter out the input capture and it is therefore not recommended to use noise canceler with these sources. 17.7 output compare unit the comparator continuously compares the ti mer/counter (tcntn) with the output compare registers (ocrna and ocrnb), and whenever the timer/counter equals to the output com- pare registers, the comparator signals a match. a match will set the output compare flag at the next timer clock cycle. in 8-bit mode the match can set either the output compare flag ocfna or ocfnb, but in 16-bit mode the match can set only the output compare flag ocfna as there is only one output compare unit. if the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. the output compare flag is automati- cally cleared when the interrupt is executed. altern atively, the flag can be cleared by software by writing a logical one to its i/o bit location. figure 17-5 on page 88 shows a block diagram of the output compare unit. figure 17-5. output compare unit, block diagram table 17-3. timer/counter0 input capture source (ics) ics0 source 0 icp00: port pb0 1 icp01: osi_posedge pin from osi module (1)(2) table 17-4. timer/counter1 input capture source (ics) ics1 source 0 icp10: battery protection interrupt (1) 1 icp11: voltage regulator interrupt (1) ocfn x (int.req.) = (8/16-bit comparator ) ocrnx data b u s tcntn 89 8042a?avr?07/09 atmega16hvb/32hvb 17.7.1 compare match bloc king by tcnt0 write all cpu write operations to the tcntnh/l regi ster will block any compar e match that occur in the next timer clock cycle, even when the timer is stopped. this feature allows ocrna/b to be initialized to the same value as tcntn withou t triggering an interrupt when the timer/counter clock is enabled. 17.7.2 using the output compare unit since writing tcntnh/l will block all compare matc hes for one timer clock cycle, there are risks involved when changing tcntnh/l when using the output compare unit, independently of whether the timer/counter is running or not. if the value written to tcntnh/l equals the ocrna/b value, the compare match will be missed. 17.8 timer/counter timing diagrams the timer/counter is a synchron ous design and the timer clock (clk tn ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set. figure 17-6 on page 89 contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max value. figure 17-6. timer/counter timing diagram, no prescaling figure 17-7 on page 89 shows the same timing data, but with the prescaler enabled. figure 17-7. timer/counter timing dia gram, with prescaler (f clk_i/o /8) figure 17-8 on page 90 shows the setting of ocfna and ocfnb in normal mode. clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) 90 8042a?avr?07/09 atmega16hvb/32hvb figure 17-8. timer/counter timing diagram, setting of ocfnx, with prescaler (f clk_i/o /8) figure 17-9 on page 90 shows the setting of ocfna and the clearing of tcntn in ctc mode. figure 17-9. timer/counter timing diagram, ctc mode, with prescaler (f clk_i/o /8) 17.9 accessing register s in 16-bit mode in 16-bit mode (the tcwn bit is set to one) the tcntnh/l and ocrna/b or tcntnl/h and ocrnb/a are 16-bit registers that can be accessed by the avr cpu via the 8-bit data bus. the 16-bit register must be byte accessed using two read or write operations. the 16-bit timer/counter has a single 8-bit register for te mporary storing of the high byte of the 16-bit access. the same temporary register is shared between all 16-bit registers. accessing the low byte triggers the 16-bit read or write operation. when the low byte of a 16-bit register is written by the cpu, the high byte stored in the temporary register, and the low byte written are both cop- ied into the 16-bit register in the same clock cycle. when the low byte of a 16-bit register is read by the cpu, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read. there is one exception in the temporary register usage. in the output compare mode the 16-bit output compare register ocrna/b is read without the temporary register, because the output compare register contains a fixed value that is only changed by cpu access. however, in 16- bit input capture mode the icrn register formed by the ocrna and ocrnb registers must be accessed with the temporary register. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before the high byte. ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk pck clk tn (clk pck /8) 91 8042a?avr?07/09 atmega16hvb/32hvb the following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. the same principle can be used directly for accessing the ocrna/b registers. note: 1. see ?about code examples? on page 8. the assembly code example returns the tcntnh/l value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers are atomic operations. if an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. assembly code example ... ; set tcntn to 0x01ff ldi r17,0x01 ldi r16,0xff out tcntnh,r17 out tcntnl,r16 ; read tcntn into r17:r16 in r16,tcntnl in r17,tcntnh ... c code example unsigned int i; ... /* set tcntn to 0x01ff */ tcntn = 0x1ff; /* read tcntn into i */ i = tcntn; ... 92 8042a?avr?07/09 atmega16hvb/32hvb the following code examples sh ow how to do an atomic read of the tcntn register contents. reading any of the ocrn register can be done by using the same principle. note: 1. see ?about code examples? on page 8. the assembly code example returns the tcntnh/l value in the r17:r16 register pair. assembly code example timn_readtcntn: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcntn into r17:r16 in r16,tcntnl in r17,tcntnh ; restore global interrupt flag out sreg,r18 ret c code example unsigned int timn_readtcntn( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* read tcntn into i */ i = tcntn; /* restore global interrupt flag */ sreg = sreg; return i; } 93 8042a?avr?07/09 atmega16hvb/32hvb the following code examples show how to do an atomic write of the tcntnh/l register con- tents. writing any of the ocrna/b registers can be done by using the same principle. note: see ?about code examples? on page 8. the assembly code example requires that the r17:r16 register pair contains the value to be writ- ten to tcntnh/l. 17.9.1 reusing the temporary high byte register if writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. however, note that the same rule of atomic operation described previously also applies in this case. assembly code example timn_writetcntn: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcntn to r17:r16 out tcntnh,r17 out tcntnl,r16 ; restore global interrupt flag out sreg,r18 ret c code example void timn_writetcntn( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* set tcntn to i */ tcntn = i; /* restore global interrupt flag */ sreg = sreg; } 94 8042a?avr?07/09 atmega16hvb/32hvb 17.10 register description 17.10.1 tccrna ? timer/counter n control register a ? bit 7? tcwn: timer/counter width when this bit is written to one 16-bit mode is se lected. timer/counter n width is set to 16-bits and the output compare registers ocrna and ocrnb are combined to form one 16-bit output compare register. because the 16-bit registers tcntnh/l and ocrnb/a are accessed by the avr cpu via the 8-bit data bus, special procedures must be followed. these procedures are described in section ?accessing registers in 16-bit mode? on page 90 . ? bit 6? icenn: input capture mode enable the input capture mode is enabled when this bit is written to one. ? bit 5 ? icncn: input capture noise canceler setting this bit activates the input capture nois e canceler. when the noise canceler is acti- vated, the input from the input capture source is filtered. the filter function requires four successive equal valued samples of the input capture source for changing its output. the input capture is therefore delayed by four system cl ock cycles when the noise canceler is enabled. ? bit 4 ? icesn: input capture edge select this bit selects which edge on the input capture source that is used to trigger a capture event. when the icesn bit is written to zero, a falling ( negative) edge is used as trigger, and when the icesn bit is written to one, a ri sing (positive) edge will trigger the ca pture. when a capture is trig- gered according to the icesn setting, the coun ter value is copied into the input capture register. the event will also set th e input capture flag (icfn), an d this can be used to cause an input capture interrupt, if this interrupt is enabled. ? bit 3 - icsn: input capture select when written logic one, this bit enables the input capture function in timer/counter n to be trig- gered by the alternative input capture source. to make the comparator trigger the timer/counter n input capture interrupt, the ticien bit in the timer interrupt mask register (timsk) must be set. see table 17-3 on page 88 and table 17-4 on page 88 . ? bits 2:0 ? res: reserved bits these bits are reserved bits in the atme ga16hvb/32hvb and will always read as zero. ? bit 0 ? wgmn0: waveform generation mode this bit controls the counting sequence of the counter, the source for maximum (top) counter value, see figure 17-6 on page 89 . modes of operation supported by the timer/counter unit are: normal mode (counter) and clear timer on compare match (ctc) mode (see ?timer/counter timing diagrams? on page 89 ). bit 76543210 0x24 (0x44) tcwn icenn icncn icesn icsn ? ? wgmn0 tccrna read/write r/w r/w r/w r/w r/w r r r/w initial value 0 0 0 0 0 0 0 0 95 8042a?avr?07/09 atmega16hvb/32hvb 17.10.2 tcntnl ? timer/counter n register low byte the timer/counter register tcntnl gives direct access, both for read and write operations, to the timer/counter unit 8-bit counter. writing to the tcntnl register blocks (disables) the com- pare match on the following timer clock. modifying the counter (tcntnl) while the counter is running, introduces a risk of missing a co mpare match between tcntnl and the ocrnx regis- ters. in 16-bit mode the tcntnl register contains the lower part of the 16-bit timer/counter n register. 17.10.3 tcntnh ? timer/counter n register high byte when 16-bit mode is selected (the tcwn bit is set to one) the timer/counter register tcntnh combined to the timer/counter register tcntnl gives direct access, both for read and write operations, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is per- formed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing registers in 16-bit mode? on page 90 . 17.10.4 ocrna ? timer/counter n output compare register a the output compare register a contains an 8-bi t value that is continuously compared with the counter value (tcntnl). a match can be used to generate an output compare interrupt. in 16-bit mode the ocrna register contains the low byte of the 16-bit output compare register. to ensure that both the high and the low bytes are written simultaneously when the cpu writes to these registers, the access is performed usi ng an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing registers in 16-bit mode? on page 90 . 17.10.5 ocrnb ? timer/counter n output compare register b the output compare register b contains an 8-bi t value that is continuously compared with the counter value (tcntnl in 8-bit mode and tcntnh in 16-bit mode). a match can be used to generate an output compare interrupt. bit 76543210 0x26 (0x46) tcntnl[7:0] tcntnl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x27 (0x47) tcntnh[7:0] tcntnh read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x28 (0x48) ocrna[7:0] ocrna read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 0x29 (0x49) ocrnb[7:0] ocrnb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 96 8042a?avr?07/09 atmega16hvb/32hvb in 16-bit mode the ocrnb register contains the high byte of the 16-bit output compare regis- ter. to ensure that both the high and the low bytes are written simultaneously when the cpu writes to these registers, the access is perf ormed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing reg- isters in 16-bit mode? on page 90 . 17.10.6 timskn ? timer/counter n interrupt mask register ? bit 3 ? icien: timer/counter n input capture interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter n input capture in terrupt is enabled. the corresponding interrupt vector ( see section ?12.? on page 52. ) is executed when the icfn flag, located in tifrn, is set. ? bit 2 ? ocienb: timer/counter n output compare match b interrupt enable when the ocienb bit is written to one, and the i-bit in the status register is set, the timer/counter compare match b interrupt is enab led. the corresponding interrupt is executed if a compare match in timer/counter occurs, i.e., when the ocfnb bit is set in the timer/counter interrupt flag register ? tifrn. ? bit 1 ? ociena: timer/counter n output compare match a interrupt enable when the ociena bit is written to one, and the i-bit in the status register is set, the timer/counter n compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter n occu rs, i.e., when the ocfna bit is set in the timer/counter n interrupt flag register ? tifrn. ? bit 0 ? toien: timer/counter n overflow interrupt enable when the toien bit is written to one, and the i-bit in the status register is set, the timer/coun- ter n overflow interrupt is enabled. the corresponding interrupt is executed if an overflow in timer/counter n occurs, i.e., when the tovn bit is set in the timer/counter n interrupt flag reg- ister ? tifrn. 17.10.7 tifrn ? timer/counter n interrupt flag register ? bits 3 ? icfn: timer/counter n input capture flag this flag is set when a capture event occurs, according to the setting of icenn, icesn and icsn bits in the tccrna register. icfn is automatically cleared when the input capt ure interrupt vector is executed. alternatively, icfn can be cleared by writing a logic one to its bit location. bit 76543210 (0x6e)(0x6f) ----icienocienbocienatoientimskn read/write r r r r r/w r/w r/w r initial value00000000 bit 76543210 0x15 (0x35) ----icfnocfnb ocfna tovn tifrn read/writerrrrr/wr/wr/wr/w initial value00000000 97 8042a?avr?07/09 atmega16hvb/32hvb ? bit 2 ? ocfnb: output compare flag n b the ocfnb bit is set when a compare match occurs between the timer/counter and the data in ocrnb ? output compare register n b. ocfnb is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocfnb is cleared by writing a logic one to the flag. when the i-bit in sreg, ocienb (timer/counter compare b match interrupt enable), and ocfnb are set, the timer/counter compare match interrupt is executed. the ocfnb is not set in 16-bit output compare mode when the output compare register ocrnb is used as the high byte of the 16-bit output compare register or in 16-bit input cap- ture mode when the output compare register ocrnb is used as the hi gh byte of the input capture register. ? bit 1? ocfna: output compare flag n a the ocfna bit is set when a compare match occurs between the timer/counter n and the data in ocrna ? output compare register n. ocfna is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, ocfna is cleared by writing a logic one to the flag. when the i-bit in sreg, ociena (timer/counter n compare match interrupt enable), and ocfna are set, the timer/counter n compare match interrupt is executed. the ocfna is also set in 16-bit mode when a compare match occurs between the timer/coun- ter n and 16-bit data in ocrnb/a. the ocfna is not set in input capture mode when the output compare register ocrna is used as an input capture register. ? bit 0 ? tovn: timer/counter n overflow flag the bit tovn is set when an overflow occurs in timer/counter n. tovn is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tovn is cleared by writing a logic one to the flag. when the sreg i-bit, toien (timer/counter n overflow interrupt enable), and tovn are set, the timer/counter n overflow interrupt is executed. 98 8042a?avr?07/09 atmega16hvb/32hvb 18. spi ? serial peripheral interface 18.1 features ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? seven programmable bit rates ? end of transmission interrupt flag ? write collision protection flag ? wake-up from idle mode ? double speed (ck/2) master spi mode 18.2 overview the serial peripheral interface (spi) allows hi gh-speed synchronous data transfer between the atmega16hvb/32hvb and peripheral devices or between several avr devices. when the spi is not used, power consumption can be minimized by writing the prspi bit in prr0 to one. see ?prr0 ? power reduction register 0? on page 40 for details on how to use the prspi bit. figure 18-1. spi block diagram (1) note: 1. refer to ?alternate port functions? on page 72 for spi pin placement. spi2x spi2x divider /2/4/8/16/32/64/128 99 8042a?avr?07/09 atmega16hvb/32hvb the interconnection between master and slave cpus with spi is shown in figure 18-2 . the sys- tem consists of two shift registers, and a master clock generator. the spi master initiates the communication cycle when pu lling low the slave select ss pin of the desired slave. master and slave prepare the data to be sent in their respective shift registers, and the master generates the required clock pulses on the sck line to interchange data. data is always shifted from mas- ter to slave on the master out ? slave in, mosi, line, and from slave to master on the master in ? slave out, miso, line. after ea ch data packet, the master will synchronize the slave by pulling high the slave select, ss , line. when configured as a master, the spi interface has no automatic control of the ss line. this must be handled by user software before communication can start. when this is done, writing a byte to the spi data register starts the spi clock generator, and the hardware shifts the eight bits into the slave. after shifting one byte , the spi clock generator stops, setting the end of transmission flag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrupt is requested. the master may continue to shift the next byte by writing it into spdr, or signal the end of packet by pulling high the slave select, ss line. the last incoming byte will be kept in the buffer register for later use. when configured as a slave, the spi interface will remain sleeping with miso tri-stated as long as the ss pin is driven high. in this state, software may update the contents of the spi data register, spdr, but the data will not be shifted out by incoming clock pulses on the sck pin until the ss pin is driven low. as one byte has been completely shifted, the end of transmission flag, spif is set. if the spi interrupt enable bit, spie, in the spcr register is set, an interrupt is requested. the slave may continue to place new data to be sent into spdr before reading the incoming data. the last incoming byte will be kept in the buffer register for later use. figure 18-2. spi master-slave interconnection the system is single buffered in the transmit di rection and double buffered in the receive direc- tion. this means that bytes to be transmitted cannot be written to the spi data register before the entire shift cycle is complet ed. when receiving data, however, a received character must be read from the spi data register before the next character has been completely shifted in. oth- erwise, the first byte is lost. in spi slave mode, the control logic will sample the incoming signal of the sck pin. to ensure correct sampling of the clock signal, the frequency of the spi clock should never exceed f osc /4. when the spi is enabled, the data direction of the mosi, miso, sck, and ss pins is overridden according to table 18-1 on page 100 . for more details on automatic port overrides, refer to ?alternate port functions? on page 72 . shift enable 100 8042a?avr?07/09 atmega16hvb/32hvb note: 1. see ?alternate functions of port b? on page 75 for a detailed description of how to define the direction of the user defined spi pins. the following code examples show how to initialize the spi as a master and how to perform a simple transmission. ddr_spi in the examples mu st be replaced by the actual data direction register controlling the spi pins. dd_mosi, dd_miso and dd_sck must be replaced by the actual data direction bits for these pins. e.g. if mosi is placed on pin pb5, replace dd_mosi with ddb5 and ddr_spi with ddrb. table 18-1. spi pin overrides (1) pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input 101 8042a?avr?07/09 atmega16hvb/32hvb note: 1. see ?about code examples? on page 8. assembly code example (1) spi_masterinit: ; set mosi and sck output, all others input ldi r17,(1< 104 8042a?avr?07/09 atmega16hvb/32hvb figure 18-3. spi transfer format with cpha = 0 figure 18-4. spi transfer format with cpha = 1 bit 1 bit 6 lsb msb sck (cpol = 0) mode 0 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 2 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 msb first (dord = 0) lsb first (dord = 1) sck (cpol = 0) mode 1 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 3 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb first (dord = 0) lsb first (dord = 1) 105 8042a?avr?07/09 atmega16hvb/32hvb 18.5 register description 18.5.1 spcr ? spi control register ? bit 7 ? spie: spi interrupt enable this bit causes the spi in terrupt to be executed if spif bit in the spsr register is set and the if the global interrupt enable bit in sreg is set. ? bit 6 ? spe: spi enable when the spe bit is written to one, the spi is enabled. this bit must be set to enable any spi operations. ? bit 5 ? dord: data order when the dord bit is written to one, the lsb of the data word is transmitted first. when the dord bit is written to zero, the msb of the data word is transmitted first. ? bit 4 ? mstr: master/slave select this bit selects master spi mode when written to one, and slave spi mode when written logic zero. if ss is configured as an input and is driven low while mstr is set, mstr will be cleared, and spif in spsr will become set. the user will th en have to set mstr to re-enable spi mas- ter mode. ? bit 3 ? cpol: clock polarity when this bit is written to one, sck is high when idle. when cpol is written to zero, sck is low when idle. refer to figure 18-3 and figure 18-4 for an example. the cpol functionality is sum- marized below: ? bit 2 ? cpha: clock phase the settings of the clock phase bit (cpha) determine if data is sampled on the leading (first) or trailing (last) edge of sck. refer to figure 18-3 and figure 18-4 for an example. the cpol functionality is summarized below: bit 76543210 0x2c (0x4c) spie spe dord mstr cpol cpha spr1 spr0 spcr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 18-3. cpol functionality cpol leading edge trailing edge 0 rising falling 1 falling rising table 18-4. cpha functionality cpha leading edge trailing edge 0 sample setup 1 setup sample 106 8042a?avr?07/09 atmega16hvb/32hvb ? bits 1, 0 ? spr1, spr0: spi clock rate select 1 and 0 these two bits control the sck rate of the dev ice configured as a master. spr1 and spr0 have no effect on the slave. the relationship between sck and the oscillator clock frequency f osc is shown in the following table: 18.5.2 spsr ? spi status register ? bit 7 ? spif: spi interrupt flag when a serial transfer is complete, the spif flag is set. an interrupt is generated if spie in spcr is set and global interrupts are enabled. if ss is an input and is dr iven low when the spi is in master mode, this will also set the spif flag. spif is cleared by hardwa re when executing the corresponding interrupt handling vector. alternatively, the spif bit is cleared by first reading the spi status register with spif set, then accessing the spi data register (spdr). ? bit 6 ? wcol: write collision flag the wcol bit is set if the spi data register (spdr) is written during a data transfer. the wcol bit (and the spif bit) are cleared by first reading the spi status register with wcol set, and then accessing the spi data register. ? bit 5:1 ? res: reserved bits these bits are reserved bits in the atme ga16hvb/32hvb and will always read as zero. ? bit 0 ? spi2x: double spi speed bit when this bit is written logi c one the spi speed (sck freque ncy) will be doubled when the spi is in master mode (see table 18-5 on page 106 ). this means that th e minimum sck period will be two cpu clock periods. when the spi is conf igured as slave, the spi is only guaranteed to work at f osc /4 or lower. table 18-5. relationship between sck and the oscillator frequency spi2x spr1 spr0 sck frequency 000 f osc / 4 001 f osc / 16 010 f osc / 64 011 f osc / 128 100 f osc / 2 101 f osc / 8 110 f osc / 32 111 f osc / 64 bit 76543210 0x2d (0x4d) spif wcol ? ? ? ? ? spi2x spsr read/write rrrrrrrr/w initial value00000000 107 8042a?avr?07/09 atmega16hvb/32hvb the spi interface on the atmega16hvb/32hvb is also used for program memory and eeprom downloading or uploading. see table 30.6 on page 211 for serial programming and verification. 18.5.3 spdr ? spi data register the spi data register is a read/write register used for data transfer between the register file and the spi shift register. writing to the register initiates data transmission. reading the regis- ter causes the shift register receive buffer to be read. bit 76543210 0x2e (0x4e) msb lsb spdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial valuexxxxxxxxundefined 108 8042a?avr?07/09 atmega16hvb/32hvb 19. coulomb counter - dedicated fuel gauging sigma-delta adc 19.1 features ? sampled system coulomb counter ? low power sigma-delta adc optimized for coulomb counting ? instantaneous current output with 3.9 ms conversion time ? 13 bit resolution (including sign bit) ? interrupt on instantaneous current conversion complete ? accumulate current output ? programmable conversion time: 128/256/512/1024 ms ? 18-bit resolution (including sign bit) ? interrupt on accumulation current conversion complete ? regular current detection mode ? programmable sampling interval: 256/512/1024/2048 ms ? programmable input voltage range 100/200mv ? allowing measurement of 20/40a @ 5 m ? offset canceling by input polarity switching 19.2 overview atmega16/32hvb features a dedicated sigma-delta adc (cc-adc) optimized for coulomb counting. by sampling the charge or discharge current flowing through an external sense resis- tor rsense, the cc-adc is used to track the flow of current going into and out of the battery cells. figure 19-1. coulomb counter block diagram the cc-adc has a programmable voltage range allowing trade-off to be made between resolu- tion, dynamic range and external sense resistor rsense. sigma delta modulator current comparator control & status registers irq 8-bit databus regular current level decimation filter decimation filter irq irq r sense pi ni polarity switcher instantaneous current register accumulate current register 109 8042a?avr?07/09 atmega16hvb/32hvb in normal conversion mode two different output values are provided, instantaneous current and accumulate current. the instantaneous current output has a short conversion time at the cost of lower resolution. the accumulate current output provides a highly accurate current measure- ment for coulomb counting. the cc-adc also provides a special regular cu rrent detection mode. this allows ultra-low power operation in power-save mode when small charge or discharge currents are flowing. for offset cancellation the polarity of the input signal could be switched run time. using this fea- ture, the internal cc-adc offset could be removed. see application note avr352. 19.3 normal operation when enabled the cc-adc continuously measures the voltage over the external sense resistor r sense . running in normal conversion mode, two data conversion outputs are provided. ? instantaneous conversion result ? accumulation conversion result the instantaneous current conversion time is fix ed to 3.9 ms (typical value) allowing the output value to closely follow the input. after each instantaneous current conversion an interrupt is generated if the in terrupt is enabled. data from conversion will be updated in th e instantaneous current registers cadicl and cadich simultaneousl y as the interrupt is given. to avoid losing conversion data, both the low and high byte must be read within a 3.9 ms timing window after the corresponding interrupt is given. when the low byte register is read, updating of the instanta- neous current register s and interrupts will be stopped until the hi gh byte is read. figure 19-2 shows an instantane ous current conversion diagram, w here data4 will be lost because data3 reading is not completed within the limited period. figure 19-2. instantaneous current conversions the accumulate current output is a high-resolution, high accuracy output with programmable conversion time selected by the cadas bits in cadcsra. the converted value is an accurate measurement of the average current flow during one conversion period. the cc-adc generates an interrupt each time a new accumulate current conversion has finished if the interrupt is enabled. data from conv ersion will be updated in the accumulation current registers - cadac0, cadac1, cadac2 and cadac3 simultaneously as the interrupt is given. to avoid losing con- version data, all bytes must be read within the selected conversion period. when the lower byte registers are read, updating of the accumulation current regi sters and interr upts will be stopped until the highest byte is read. figure 19-3 shows an accumulation current conversion example, where data4 will be lost because data3 readin g is not completed wit hin the limited period. enable instantaneous interrupt instantaneous data invalid data data 1 data 2 data 3 data 5 read high byte 3.9 ms 3.9 ms ~12 ms settling 7.8 ms read low byte 110 8042a?avr?07/09 atmega16hvb/32hvb figure 19-3. accumulation current conversions 19.4 regular current detection operation by setting the cadse bit in cadcsra the cc-a dc will enter a special regular current detec- tion sampling mode. in this mode the cc-adc will do one instan taneous current conversi on on regular sampling intervals while updating of the accumulation current register is automatically disabled. the sampling interval is controlled by wr iting to the cadsi bits in cadcsra. each time a conversion is completed the result is compared with regular charge/discharge threshold levels specified in the cadrcc/cadrdc registers. if interrup t is enabled and the voltage is above/below the specified limit a re gular current detection interrupt will be issued. figure 19-4 illustrates the regular current detection mode. figure 19-4. regular current detection mode (cadse=1) 19.5 offset canceling by polarity switching the cc-adc offers polarity switch ing for internal offset cancelin g. by switching the polarity of the sampled input signal at select ed time intervals, the internal voltage offset of the cc-adc will cancel at the output. this feature prevents the cc-adc from accumulating an offset error over time. enable accumulation interrupt accumulation data invalid data data 1 data 2 data 3 data 5 read byte 1 read byte 2 read byte 3 read byte 4 125, 250, 500, or 1000 ms 125, 250, 500, or 1000 ms 1, 2, 3, or 4s settling 250, 500, 1000, or 2000 ms measure turn-off ~12ms ~250, 500, 1000, 2000ms measure ~12ms turn-off ~250, 500, 1000, 2000ms regular current detection operation regular current detection interupt regular charge current threshold regular discharge current threshold current through r sense 111 8042a?avr?07/09 atmega16hvb/32hvb 19.6 configuration and usage while the cc-adc is converting, the cpu can enter sleep mode and wait for an interrupt. after adding the conversion data for the coulomb counting, the cpu can go back to sleep again. this reduces the cpu workload, and allows more time spent in low power modes, reducing power consumption. to use the cc-adc the bandgap voltage reference must be enabled separately, see ?voltage reference and temperature sensor? on page 123 . the cc-adc will not consume power when cade n is cleared. it is therefore recommended to switch off the cc-adc whenever the coulomb counter or regular current detection functions are not used. the cc-adc is automatically disabled in power-off mode. after the cc-adc is enabled by setting the caden bit, the first four conversions do not contain useful data and should be ignored. this also applies after clearing the cadse bit, or after changing the cadpol or cadvse bits. the conversion times and samplin g intervals are controlled by the ultra low power rc oscilla- tor (see ?ultra low power rc oscillator? on page 27 ), and will depend on its actual frequency. to obtain accurate coulomb counting results, the actual conversion time should be calculated. refer to ?system clock and clock options? on page 25 for details. 19.7 register description 19.7.1 cadcsra ? cc-adc control and status register a ? bit 7 ? caden: cc-adc enable when the caden bit is cleared (zero), the cc-adc is disabled, and any ongoing conversions will be terminated. when the caden bit is set (o ne), the cc-adc will continuously measure the voltage drop over the external sense resistor r sense . in power-off, the cc-adc is always disabled. note that the bandgap voltage reference must be enabled separately, see ?voltage reference and temperature sensor? on page 123 . ? bit 6 ? cadpol: cc-adc polarity the cadpol bit is used to change input sampling polarity in the sigma de lta modulator. writing this bit to one, the polaritiy will be negative. when the bit is zero, the polarity will be positive. ? bit 5 - cadub: cc-adc update busy the cc-adc operates in a different clock domain than the cpu. whenever a new value is writ- ten to cadcsra, cadcsrc, cadrcc or cadrdc, this value must be synchronized to the cc-adc clock domain. subsequent writes to th ese registers will be blocked during this synchro- nization. synchronization of on e of the registers will block updat ing of all the others. the cadub bit will be read as one while any of these registers is being synchronized, and will be read as zero when neither register is being synchronized. bit 76543210 (0xe6) caden cadpol cadub cadas1 cadas0 cadsi1 cadsi0 cadse cadcsra read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 112 8042a?avr?07/09 atmega16hvb/32hvb ? bits 4:3 ? cadas1:0: cc-adc accumulate current select the cadas bits select the conversion time for the accumulate current output as shown in the table 19-1 . note: 1. the actual value of depends on the actual frequency of the ?ultra low power rc oscillator? on page 27 . see section ?32.? on page 228. ? bits 2:1 ? cadsi1:0: cc-adc current sampling interval the cadsi bits determine the current sampling interval for the regular current detection as shown in the table 19-2 . notes: 1. the actual value of depends on the actual frequency of the ?ultra low power rc oscillator? on page 27 . see ?electrical characteristics? on page 228. 2. sampling time ~ 12 ms. ? bit 0 ? cadse: cc-adc sampling enable when the cadse bit is written to one, the ongoing cc-adc conversion is aborted and the cc- adc enters regular current detection mode. 19.7.2 cadcsrb ? cc-adc control and status register b ? bits 7, 3 ? res: reserved these bits are reserved bits in the atme ga16hvb/32hvb and will always read as zero. ? bit 6 ? cadacie: cc-adc accumu late current interrupt enable when the cadacie bit is set (one), and the i-bit in the status register is set (one), the cc-adc accumulate current interrupt is enabled. table 19-1. cc-adc accumulate cu rrent conversion time cadas1:0 cc-adc accumulate current conversion time (1) number of cc-adc clock cycles 00 128 ms 4096 01 256 ms 8192 10 512 ms 16384 11 1 s 32768 table 19-2. cc-adc regular current sampling interval cadsi1:0 cc-adc regular current sampling interval (1)(2) number of cc-adc clock cycles 00 256 ms (+ sampling time ) 8192 (+ sampling time) 01 512 ms (+ sampling time) 16384 (+ sampling time) 10 1 s (+ sampling time) 32768 (+ sampling time) 11 2 s (+ sampling time) 65536 (+ sampling time) bit 7 6 5 4 3 2 1 0 (0xe7) ? cadacie cadrcie cadicie ? cadacif cadrcif cadicif cadcsrb read/write r r/w r r/w r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 113 8042a?avr?07/09 atmega16hvb/32hvb ? bit 5 ? cadrcie: cc-adc regu lar current interrupt enable when the cadrcie bit is set (one), and the i-bit in the status register is set (one), the cc-adc regular current interrupt is enabled. ? bit 4 ? cadicie: cc-adc instan taneous current interrupt enable when the cadicie bit is set (one), and the i-bit in the status register is set (one), the cc-adc instantaneous current interrupt is enabled. ? bit 2 ? cadacif: cc-adc accumulate current interrupt flag the cadacif bit is set (one) after the accumulate current conversion has completed. the cc- adc accumulate current interrupt is executed if the cadacie bit and the i-bit in sreg are set (one). cadacif is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, cadacif is cleared by writing a logic one to the flag. ? bit 1 ? cadrcif: cc-adc regular current interrupt flag the cadrcif bit is set (one) when the absolute va lue of the result of the last cc-adc conver- sion is greater than, or equal to, the compare values set by the cc-adc regular charge/discharge current level registers. a positive value is compared to the regular charge current level, and a negative value is compared to the regular discharge current level. the cc-adc regular current in terrupt is executed if the cadrcie bit and the i-bit in sreg are set (one). cadrcif is cleared by hardware when ex ecuting the corresponding interrupt handling vector. alternatively, cadrcif is cleared by writing a logic one to the flag. ? bit 0 ? cadicif: cc-adc instan taneous current interrupt flag the cadicif bit is set (one) when a cc-adc instantaneous current conversion is completed. the cc-adc instantaneous current interrupt is executed if the cadicie bit and the i-bit in sreg are set (one). cadicif is cleared by hardware when executing the corresponding inter- rupt handling vector. alternatively, cadicif is cleared by writing a logic one to the flag. 19.7.3 cadcsrc ? cc-adc control and status register c ? bit 7:1 ? res: reserved these bits are reserved bits and will always read as zero. ? bit 0 ? cadvse: cc-adc voltage scaling enable setting this bit enables the internal voltage scaling. when enabling the internal voltage scaling the internal cc-adc reference will be divided by 2, affecting the input voltage range and the resulting step-size. table 19-3 shows the input voltage range and the conversion value step- size for the ca dvse settings. bit 7 6 5 4 3 2 1 0 (0xe8) ? ? ? ? ? ? ? cadvse cadcsrc read/write r r r r r r r r/w initial value 0 0 0 0 0 0 0 0 114 8042a?avr?07/09 atmega16hvb/32hvb 19.7.4 cadich and cadicl ? cc- adc instantaneous current when a cc-adc instantaneous current conversion is complete, the result is found in these two registers. cadic15:0 represents the converted result in 2's complement format. bits 12:0 are the 13-bit adc result (including sign), while bit 15:13 are the sign extension bits. when cadicl is read, the cc-a dc instantaneous current register is not updated until cadch is read. reading the registers in the sequence cadicl, cadich will ensure that consistent val- ues are read. when a conversion is completed, both registers must be read before the next conversion is completed, otherwise data will be lost. 19.7.5 cadac3, cadac2, cadac1 and cadac0 ? cc-adc accumulate current the cadac3, cadac2, cadac1 and cadac0 registers contain the accumulate current measurements in 2?s complement format. bits 17:0 are the 18-bit adc result (including sign), while bit 31:18 are the sign extension bits. when cadac0 is read, the cc-a dc accumulate current register is not updated until cadac3 is read. reading the registers in the se quence cadac0, cadac1, cadac2, cadac3 will ensure that consistent values are read. when a conversion is completed, all four registers must be read before the next conversion is completed, otherwis e data will be lost. table 19-3. input voltage range and the conversi on value step-size for the cadvse settings. cadvse voltage range step-size cadac step-size cadic 0 200 mv 1.67 v 53.7 v 1 100 mv 0.84 v 26.9 v bit 151413121110 9 8 (0xe5) cadic[15:8] cadich (0xe4) cadic[7:0] cadicl bit 76543210 read/write rrrrrrrr rrrrrrrr initial value 0 0 0 0 0 0 0 0 00000000 bit 3130292827262524 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 (0xe3) cadac[31:24] cadac3 (0xe2) cadac[23:16] cadac2 (0xe1) cadac[15:8] cadac1 (0xe0) cadac[7:0] cadac0 read/write rrrrrrrr rrrrrrrr rrrrrrrr initial value 00000000 00000000 00000000 115 8042a?avr?07/09 atmega16hvb/32hvb 19.7.6 cadrcc ? cc-adc regular charge current the cc-adc regular charge current register determines the threshold level for the regular charge current detection. when the result of a cc-adc instantaneous current conversion is positive with a value greater than, or equal to, the regular charge current level, the cc-adc regular current interrupt flag is set. the value in this register defines the eight l east significant bits of the regular charge current level in 2's complement format, where the most significant bits of the regular charge current level are always zero. the programmable range for the regular charge current level is given in the table 19-4 . note: 1. values in the table are shown with the cadvse set to both 0 and 1. the cc-adc regular charge current register does not affect the setting of the cc-adc con- version complete interrupt flag. 19.7.7 cadrdc ? cc-adc regular discharge current the cc-adc regular discharge current register determines the threshold level for the regular discharge current detection. when the result of a cc-adc instantaneous current conversion is negative with an absolute value greater than, or equal to, the regular discharge current level, the cc-adc regular current interrupt flag is set. the value in this register defines the eight least significant bits of the regular discharge current level in 2's complement format, where the most significant bits of the regular discharge current level are always one. the programmable range for the regular discharge current level is given in the table 19-5 . bit 76543210 (0xe9) cadrcc[7:0] cadrcc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 19-4. programmable range for the regular charge current level (1) minimum maximum step size voltage (v) 0 13696/6848 53.7/26.9 current (ma) r sense = 1 m 0 13696/6848 53.7/26.9 r sense = 5 m 0 2740/1370 10.7/5.4 r sense = 10 m 0 1370/685 5.3/2.7 bit 7 6 5 43210 (0xea) cadrdc[7:0] cadrdc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value0 0 0 00000 116 8042a?avr?07/09 atmega16hvb/32hvb note: 1. values in the table are shown with the cadvse set to both 0 and 1. the cc-adc regular discharge current register does not affect the setting of the cc-adc conversion complete interrupt flag. table 19-5. programmable range for the regular discharge current level minimum maximum step size voltage (v) 0 13696/6848 53.7/26.9 current (ma) r sense = 1 m 0 13696/6848 53.7/26.9 r sense = 5 m 0 2740/1370 10.7/5.4 r sense = 10 m 0 1370/685 5.3/2.7 117 8042a?avr?07/09 atmega16hvb/32hvb 20. voltage adc ? 7-channel genera l purpose 12-bit sigma-delta adc 20.1 features ? 12-bit resolution ? 519s conversion time @ 1 mhz clk vadc ? four differential input channels for cell voltage measurements ? three single ended input channels ? 0.2x pre-scaling of cell voltages ? interrupt on v-adc conversion complete 20.2 overview the atmega16hvb/32hvb features a 12-bit sigma-delta adc. the voltage adc (v-adc) is connected to seven different sources through the input multi- plexer. there are four differential channels for cell voltage measurements. these channels are scaled 0.2x to comply with the full scale range of the v-adc. in addition there are three single ended channels referenced to sgnd. one channel is for measuring the internal temperature sensor vptat and two channels for measuring the voltage at adc0 and adc1. when the v-adc is not used, power consumptio n can be minimized by writing the prvadc bit in prr0 to one. see ?prr0 ? power reduction register 0? on page 40 for details on how to use the prvadc bit. figure 20-1. voltage adc block schematic 20.3 operation to enable v-adc conversions, the v-adc enable bit, vaden, in v-adc control and status register ? vadcsr must be set. if this bit is cleared, the v-adc will be switched off, and any ongoing conversions will be terminated. the v-adc is automati cally disabled in power-save and v-adc conversion complete irq 8-bit data bus v-adc multiplexer sel. reg (vadmux) v-adc control and status reg (vadcsr) v-adc data register (vadcl/adch) vadccie vadccif 12-bit sigma-delta adc input mux v-adc control adc1/sgnd adc0/sgnd vtemp pv2 pv1 nv note: the shaded signals are scaled by 0.2, other signals are scaled by 1.0 vref sgnd pv3 pv4 118 8042a?avr?07/09 atmega16hvb/32hvb power-off mode. note that the bandgap voltage reference must be enabled and disabled sepa- rately, see ?bandgap calibration? on page 124 . figure 20-2. voltage adc conversion diagram to perform a v-adc conversion, the analog input c hannel must first be selected by writing to the vadmux register. when a logical one is writt en to the v-adc start conversion bit vadsc, a conversion of the selected channel will start. the vadsc bit stays high as long as the conver- sion is in progress and will be cleared by hardw are when the conversion is completed. when a conversion is in progress, the v-adc data r egister - vadcl and vadch will be invalid. if the system clock prescaler settin g is changed during a v-adc conversion, the conversion will be aborted. if a different data chan nel is selected while a conversion is in progress, the adc will fin- ish the current conversion before performing the channel change. when a conversion is finished the v-adc conversion complete interrupt flag ? vadccif is set. one 12-bit conversion takes 519 s to complete from the start bit is set to the interrupt flag is set. the v-adc data register - vadcl and vadch will be valid until a new conversion is started. to ensu re that correct data is read, both high and low byte data registers should be read before starting a new conversion. 20.3.1 configuring pa1 and pa0 for v-adc operation when one of the single ended channels adc0 or adc1 is used as analog input to the vadc, either pa0 or pa1 are used as signal ground (sgnd). when adc0/1 is selected as input chan- nel, pa1/0 is automatica lly switched to sgnd. the use of pa1 and pa0 as sgnd is efficient for the thermistor configuration shown in ?operat- ing circuit? on page 225 . both thermistors, rt33 and rt34 are connected through a common divider resistor, r32, to pa0 and pa1 respectively. both pa0 and pa1 have very high input impedance when used as adc inputs, which makes it possible to connect two thermistors in the configuration, shown in ?operating circuit? on page 225 . however, input impedance is limited and if high accuracy is required, only one thermistor should be connected between pa0 and pa1. if two thermistors are connected, the configuration is as follows: ? when measuring rt34, pa1 should be used as input channel and pa0 is automatically switched to sgnd. ? when measuring rt33, pa0 should be used as input channel and pa1 is automatically switched to sgnd. start conversion interrupt conversion result invalid data invalid data old data valid data 119 8042a?avr?07/09 atmega16hvb/32hvb 20.3.2 cell inputs the v-adc features one input channel for each battery cell to be able to measure each cell indi- vidually and to measure the total battery voltage through the input pins nv, pv1, pv2, pv3 and pv4. note that the internal cell balancing uses the same pins to bypass balancing current ( see ?cell balancing? on page 154. ) for details for balancing the battery cells. when balancing a cell the v-adc should not do conversion on the sele cted channel, as the in ternal cell balancing will affect the conversion result. the v-adc is designed to operate on pv1 pin voltages above 2v. if the battery cell voltage on pv1 input falls below 2v the upper cell voltage appears to be lower than the its actual value. to avoid that cells get potentially overcharged soft ware should keep the cells in balance using the internal cell balancing. see ?cell balancing? on page 154. for details. when not using all the cell inputs, the unused cells should be connected to the cell below. an example external coupling in 3-cell mode is shown in figure 20-3 on page 119 . note that even if the input is not used, it is recommended to connect the input through an external resistance to limit inverse coupling current. this is to be able to protect the battery if cells are reversed cou- pled during production. figure 20-3. 1 3-cell mode connection atmega16hvb/32hvb r r pv4 pv3 pv2 pv1 nv r c c c r r 120 8042a?avr?07/09 atmega16hvb/32hvb 20.4 register description 20.4.1 vadmux ? v-adc multiplexer selection register ? bit 7:4 ? res: reserved bits these bits are reserved bits in the atme ga16hvb/32hvb and will always read as zero. ? bit 3:0 ? vadmux3:0: v- adc channel selection bits the vadmux bits determine the v-adc channel selection. see table 20-1 on page 120 . 20.4.2 vadcsr ? v-adc cont rol and status register ? bit 7:4 ? res: reserved bits these bits are reserved bits in the atme ga16hvb/32hvb and will always read as zero. ? bit 3 ? vaden: v-adc enable writing this bit to one enables v-adc conversion. by writing it to zero, the v-adc is turned off. turning the v-adc off while a conversion is in progress will te rminate this conv ersion. note that the bandgap voltage reference must be enabled separately, see ?bandgap calibration? on page 124. ? bit 2 ? vadsc: voltage adc start conversion write this bit to one to start a new conversion of the selected channel. bit 7654 3 2 1 0 (0x7c) ????vadmux3vadmux2vadmux1vadmux0vadmux read/write r r r r r/w r/w r/w r/w initial value0000 0 0 0 0 table 20-1. vadmux channel selection vadmux3:0 channel selected scale 0000 reserved ? 0001 cell 1 0.2 0010 cell 2 0.2 0011 cell3 0.2 0100 cell4 0.2 0101 vtemp 1.0 0110 adc0 1.0 0111 adc1 1.0 1000...1111 reserved ? bit 76543210 (0x7a) ?? ? ? vaden vadsc vadcci f vadccie vadcsr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 121 8042a?avr?07/09 atmega16hvb/32hvb vadsc will read as one as long as the conversion is not finished. when the conversion is com- plete, it returns to zero. writing zero to this bit has no effect. vadsc will automatically be cleared when the vaden bit is written to zero. ? bit 1 ? vadccif: v-adc conversion complete interrupt flag this bit is set when a v-adc conversion completes and the data registers are updated. the v- adc conversion complete interrupt is executed if the vadccie bit and the i-bit in sreg are set. vadccif is cleared by hardware when executing the corresponding interrupt handling vec- tor. alternatively, vadccif is cl eared by writing a logical one to the flag. beware that if doing a read-modify-write on vadcsr, a pending interrupt can be lost. ? bit 0 ? vadccie: v-adc conver sion complete interrupt enable when this bit is written to one and the i-bit in sreg is set, the v-adc conversion complete interrupt is activated. 20.4.3 vadcl and vadch ? v-adc data register when a v-adc conversion is complete, the result is found in these two registers. to ensure that correct data is read, both high and low byte data registers should be read before starting a new conversion. ? vadc11:0: v-adc conversion result these bits represent the result from the conversion. to obtain the best absolute accuracy for the cell voltage measurements, gain and offset com- pensation is required. factory calibration values are stored in the device signature row, refer to section ?reading the signature row from software? on page 199 for details. the cell voltage in mv is given by: the voltage on the adcn is given by: when performing a vtemp conversion, the result must be adjusted by the factory calibration value stored in the signature row, refer to section ?reading the signature row from software? on page 199 for details. the absolute temperature in kelvin is given by: bit 15 14 13 12 11 10 9 8 (0x79) ? ? ? ? vadc[11:8] vadch (0x78) vadc[7:0] vadcl 76543210 read/write r r r r r r r r rrrrrrrr initial value 0 0 0 0 0 0 0 0 00000000 cell n [mv] (vadch/l vadc cell n offset) vadc cell n gain calibration word ? ? 16384 ------------------------------------------------------------------------------------------------------------------------------- ------------------------------------------------------- = adcn[mv] 1 10 ------ (vadch/l vadc adcn offset) vadc adcn gain calibration word ? ? 16384 ------------------------------------------------------------------------------------------------------------------------------- --------------------------------------------------------------- ? = 122 8042a?avr?07/09 atmega16hvb/32hvb 20.4.4 didr0 ? digital in put disable register 0 ? bits 7:2 ? res: reserved bits these bits are reserved for future use. to ensure compatibility with future devices, these bits must be written to zero when didr0 is written. ? bit 1:0 ? pa1did:pa0did: digital input disable when this bit is written logic one, the digital input buffer on the corresponding port a pin is dis- abled. the corresponding pin regist er bit will always read as zero when this bit is set. when an analog signal is applied to the pa1:0 pin and the di gital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. t(k) vadch/l vptat cal ? 16384 -------------------------------------------------------------- - = bit 765432 1 0 (0x7e) ? ? ? ? ? ? pa1did pa0did didr0 read/write r r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 123 8042a?avr?07/09 atmega16hvb/32hvb 21. voltage reference and temperature sensor 21.1 features ? accurate voltage reference of 1.100v ? voltage reference calibration interface ? internal temperature sensor ? external decoupling for optimum noise performance ? short circuit detection on th e external decoupling pin ? low power consumption 21.2 overview atmega16hvb/32hvb features a highly accurate low power on-chip bandgap reference volt- age, vref of 1.100v. this reference voltage is used as reference for the on-chip voltage regulator, the brown-out detector, the internal cell balancing, the battery protection, the v- adc and the cc-adc. figure 21-1 shows an overview of the on-chip voltage reference. figure 21-1. bandgap reference voltage in addition to the bandgap reference voltage, the voltage reference includes a calibration unit that enables run time calibration of the refere nce voltage, an on-chip temperature sensor for monitoring the die temperature, and a bandgap short detector to detect short circuit conditions on the external vref pin for highest safety. bg calibration bg control and status 8-bit databus bangap reference w/ temperature sensor bg short detector vref vrefgnd irq vptat 1.1v bg buffer 124 8042a?avr?07/09 atmega16hvb/32hvb 21.3 operation when the device is in po wer-off state, the voltage reference will be switched off. after a power- on reset condition the voltage reference will autom atically be enabled. by default the bandgap buffer will be enabled as the buffered refer ence voltage is used as refer- ence for the battery protection, the internal ce ll balancing, the v-adc and the cc-adc. if any of these modules are enabled the bandgap buffer must be enabled, otherwise it is recom- mended to disable the buffer by writing to the bgd bit in bgcsr to save power. note that the bandgap buffer needs settling time before the voltage is stable. for details on settling time, see ?bandgap buffer settling time? on page 125 . to ensure that the battery protection has safe operation condition, the voltage reference includes a short-circuit detector. the bandgap short detector continuously monitors the internal 1.100v reference voltage against the vref pin volt age to detect potentially external short condi- tions to vcc or gnd. if an external shor t condition is detected, the bandgap short circuit detection is capable of interrupting and waking up the cpu from any sleep mode. if a bandgap short-circuit condition occurs software should immediately disable the c-fet and d-fet. if no external protection is provided to detect su ch a condition it is recommended to always enable this feature, by setting the bgscde bit in the bandgap control and status register. the temperature sensor generates a voltage proportional-to-absolute-temperature, vptat. this voltage is connected to the multiplexer at the v-adc input and it can be used for runtime compensation of temperature drift in both the voltage reference and the on-chip oscillator. to get the absolute temperature in degrees kelvin, the measured vptat voltage must be scaled with the vptat factory calibration value stored in the signature row. see ?reading the signature row from software? on page 199 for details. see ?electrical characteristics? on page 228 for details on temperature accuracy. 21.4 bandgap calibration to guarantee ultra low temperature drift the voltage reference includes two calibration registers that could be changed run-time by software. changing values to the bgccr io register will change the nominal value of the bandgap refer ence voltage, while changing values to the bgcrr io register trims the temperature gradient of the bandgap reference. when the calibration registers are changed it will affect both t he voltage regulator output and bod-level. the bod will react quickly to new detecti on levels, while the re gulator will adjust the voltage more slowly, depending on the size of th e external decoupling capacitor. to avoid that a bod-reset is issued when calibration is done, it is recommended to change the values of the bgcc and bgcr bits stepwise, with a step size of 1, and with a hold-off time between each step. see ?electrical characteristics? on page 228 for details on hold-off time. changing vref will influence the conversion re sults for the v-adc and cc-adc. it is therefore not recommended to do v-adc and cc-adc conversions while calibrating the bandgap. to guarantee ultra low temperature drift it is recommended to perform factory calibration using a two-step calibration algorithm. by default, atmel factory calibration is performed at hot tempera- ture, and the result is stored in the signature row. see ?reading the signature row from software? on page 199 for details. the customer can easily implement the second calibration step in their test flow. 125 8042a?avr?07/09 atmega16hvb/32hvb 21.5 bandgap buffer settling time after the voltage reference have been enabled it needs a settling time before the voltage is sta- ble. the settling time depends on the size of the external decoupling capacitor. with 1uf external capacitor a minimum settling time of 2ms should be used. until settling is done it is not recommended to enable the nfet driver (oc/od or enter duvr operation), battery protection, v-adc or cc-adc. settling time is needed when the buffer is enabled by software, or after a reset condition where the buffer is automatically enabled. 126 8042a?avr?07/09 atmega16hvb/32hvb 21.6 register description 21.6.1 bgccr - bandgap calibration c register ? bits 7:6 - res: reserved bits these bits are reserved bits and will always read as zero. ? bit 5:0 - bgcc5:0: bg calibration of ptat current these bits are used for trimming of the nomina l value of the bandgap reference voltage. these bits are binary coded. minimum vref: 000000, maximum vref: 111111. step size is approxi- mately 2 mv. 21.6.2 bgcrr - bandgap calibration r register ? bit 7:0 - bgcr7:0: bg calibration of resistor ladder these bits are used for temperature gradient adjustment of the bandgap reference. figure 21-2 illustrates vref as a function of temperature. vref has a positive temperature coefficient at low temperatures and negative temperature coefficient at high temperatures. depending on the process variations, the top of the vref curve may be located at higher or lower temperatures. to minimize the temperat ure drift in the temperat ure range of interest, bgcrr is used to adjust the top of the curve towards the centre of the temperature range of interest. the bgcrr bits are thermometer coded, resulting in 9 possible settings: 00000000, 00000001, 00000011, 00000111, ? , 11111111. the value 00000000 shifts the top of the vref curve to the highest possible temperature, and the value 11111111 shifts the top of the vref curve to the lowest possible temperature. bit 7 6 5 4 3 2 1 0 (0xd0) - - bgcc5 bgcc4 bgcc3 bgcc2 bgcc1 bgcc0 bgccr read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 (0xd1) bgcr7 bgcr6 bgcr5 bgcr4 bgcr3 bgcr2 bgcr1 bgcr0 bgcrr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 1 1 1 1 127 8042a?avr?07/09 atmega16hvb/32hvb figure 21-2. 21.6.3 bgcsr - bandgap control and status register ? bits 7:6 - res: reserved bits these bits are reserved bits and will always read as zero. ? bit 5 -bgd: bandgap disable setting this bit to one will disable the bandgap volt age reference. this bit must be cleared (zero) before enabling cell balancing, cc-adc, v-adc or battery protection, and must remain unset (zero) while either of these modules are enabled. note that after clearing this bit, a settling time is required before the voltage is stable, see ?bandgap buffer settling time? on page 125 . ? bit 4 - bgscde: bandgap shor t circuit detection enabled setting this bit to one will enable the bandgap short circuit detector. this bit should be cleared if the bgd bit in the bgcsr is set to one to avoid false setting of the bgscdif bit. ? bits 3:2 - res: reserved bits these bits are reserved bits and will always read as zero. ? bit 1 - bgscdif: bandgap short circuit detection interrupt flag the bit is set when the bandgap short circui t detector is enabled and buffered bandgap refer- ence is different from the unbuffered bandgap reference. the bgscdif is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, bgscdif is cleared by writing a logic one to its bit position. bit 7 6 5 4 3 2 1 0 (0xd2) - - bgd bgscde - - bgscdif bgscdie bgcsr read/write r r r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 128 8042a?avr?07/09 atmega16hvb/32hvb ? bit 0 - bgscdie: bandgap short ci rcuit detection interrupt enable when this bit is set, the bandgap short circuit detection interrupt is enabled. the corresponding interrupt is executed if a short-circuit is detec ted on the external decoupling pin for the voltage reference. 129 8042a?avr?07/09 atmega16hvb/32hvb 22. charger detect 22.1 features ? operates directly from vfet supply ? detects when a charger is connected or di sconnected by monitoring the batt pin ? controls the operation st ate of the device by au tomatically enable/disable the internal voltage regulator ? automatically disabled when discharge fet is on. ? interrupt wake-up from all sleep modes 22.2 overview the charger detect module has two main functions: ? control the device operating state (power-off or normal operation) ? detect when a charger is connected/disconnected figure 22-1 shows a block diagram of the charger detect module. figure 22-1. charger detect block diagram. charger detect w/power-on reset vfet + - irq power_off por 8-bit databus dfet_en blod sleep (power-off) batt charger detect interrupt logic charger_present 130 8042a?avr?07/09 atmega16hvb/32hvb 22.3 operation the charger detect module is supplied directly from the vfet pin. when operating, the charger detect will monitor the voltage of the batt pi n and detect whether a charger is present or not. when the voltage on the batt pin is above the charger detect threshold level v pot ( ?electrical characteristics? on page 228 ) the charger_present signal will be high. this signal is edge detected to generate interrupt when a charger is connected or disconnected. the charger detect module will o perate as long as the discharge fet is disabled and is able to detect a charger in all sleep modes including power-off. 22.3.1 device operating state the charger detect module controls the operating state of the atmega16hvb/32hvb by enabling/disabling the voltage regulator, which supplies the rest of the internal logic on the chip. if the chip is in power-off state the charger detect will keep the voltage r egulator disabled allowing only the charger detect module itself to operate. to be able to start from a power-off state a charge voltage above v pot has to be applied at the batt pin. when a charger is con- nected the charger detect module will automatic ally start the voltage regulator. when the vreg voltage rises, a power-on reset (por) is given and the chip enters normal operating mode after a reset delay corresponding to t tout . for details on por, see ?power-on reset and charger connect? on page 43 . when the atmega16hvb/32hvb is running in normal operation mode software or hardware could take the chip into power-off state. for details on entering power-off by software, see ?power-off mode? on page 38 . to protect the device against software malfunctions the atmega16hvb/32hvb has a black-out detector (blod). when a black-out condition occurs the charger detect will take the chip automatically into power-off. for details on black-out detection, see ?voltage regulator? on page 132 . note that after a software power-off the batt pin voltage has to fall below the charger detect threshold limit, vpot, before the chip is able to re-enable the voltage regulator and start-up the device. 22.3.2 interrupt logic when the atmega16hvb/32hvb is running in normal operation mode, the charger detect is capable of giving an interrupt to the cpu if a charger is connected/disconnected or both. inter- rupt is enabled/disabled by writ ing to the chgdie bit in the ?chgdcsr - ch arger detect control and status register? on page 131 . interrupt is given when a charger is connected, disconnected or both depending on interrupt sense control settings. selecting the correct interrupt sensing is done by writing to the chgdisc bits in the ?chgdcsr - charger detect control and status register? on page 131 . charger detect interr upt works asynchronous and will wake the cpu from any sleep mode. the charger detect is automatically disabled/enabled when changing the state of the discharge fet, and any interrupt that occurs when enab ling or disabling the discharge fet has to be carefully interpreted. ? when enabling the discharge-fet the charger detect module is automatically disabled. when disabling the charger detect module a charger appear to be disconnected even if a charger is present. 131 8042a?avr?07/09 atmega16hvb/32hvb ? when disabling the charge-fet the charger detect module is automatically enabled and a charger appear to be connected. 22.4 register description 22.4.1 chgdcsr - charger detect control and status register ? bit 7:5 - res: reserved these bits are reserved bits and will always read as zero. ? bit 4 - battpvl: batt pin voltage level battpvl will read one as long when the charger detect module is enabled and the batt pin voltage is above the vpot level. otherwise the battpvl will read zero. ? bit 3:2 - chgdisc1:0: charger detect interrupt sense control edges in the charger_present signal shown in figure 22-1 on page 129 are used to acti- vate a charger detect interrupt if the sreg i-flag and the interrupt enable bit in chgdcsr are set. by writing the chgdisc bits to the values shown in table 22-1 on page 131 the condition generating interrupt is configured. when changing the chgdisc bits, an interrupt can occur. therefore, it is recommended to first disable the interrupt by clearing its chgdie bit in the chgdicsr register. finally, the charger detect interrupt flag should be cleared by writing a logical one to chgdif bit before the interrupt is re-enabled. ? bit 1 - chgdif: charger detect interrupt flag depending on the configuration of the chgdisc bits in the chgdcsr, this bit is set when a charger is either connected or disconnected. the charger detect interrupt is executed if the chgdie bit and the i-bit in sreg are set. this bit is cleared by hardware when executing the corresponding interrupt handling vector or alternatively by writing a logical one to the chgdif. it is recommended to write this bit to one when setting chgdie. ? bit 0 - chgdie: charger detect interrupt enable when the chgdie bit is set (one), and the i-bit in the status register is set (one), the charger detect interrupt is enabled. bit76543210 (0xd4) - - - battpvl chgdisc1 chgdisc 0 chgdif chgdie chgdcsr read/write r r r r r/w r/w r/w r/w initial value00000000 table 22-1. charger detect interrupt sense control. chgisc1:0 detection 00 charger connect 01 charger disconnect 10 charger connect/disconnect 11 none 132 8042a?avr?07/09 atmega16hvb/32hvb 23. voltage regulator 23.1 features ? input voltage from 4-25v ? fixed output voltage of 3.3v ? battery pack short detection ? black-out detection (blod) 23.2 overview atmega16hvb/32hvb get its voltage supply through the vfet terminal. operating range at the vfet terminal is 4 - 25v. the on-chip ldo regulator regulates the vfet terminal down to 3.3v, which is a suitable supply voltage for the internal logic, i/o lines and analog circuitry. figure 23- 1 illustrates the vo ltage regulator. figure 23-1. voltage regulator. to ensure safe operating condition the voltage regulator has built in protection mechanisms to protect the internal circuitry if the voltage drops on either the input or output terminal. the regu- lator monitoring includes ? battery pack short detector ? black-out detector an external decoupling capacitor (creg) of minimum 1 f is needed to ensure stable regulator operation. the same capacitor also serves as a reservoir capacitor to ensure that the chip is able to operate for some time without voltage at the vfet terminal. regulator monitor and control interface ldo regulator databus vfet disable vfet irq blod power-off creg vreg battery short detect rocr black-out detect enable 133 8042a?avr?07/09 atmega16hvb/32hvb 23.3 regulator start-up when the chip is in power-of f mode the voltage regulator will be off and there will be no con- nection between vfet and vreg. the regulator is started when the charger detect module detects that a charger is connected (for details on charger detect, see ?charger detect? on page 129 ). when starting the regulator the voltage regulator will stay in a force mode where the vreg output is raised against the vfet input voltage. as vreg in creases to the target voltage le vel the regulato r will automati- cally enter regulation mode, with a stable output voltage of nominally 3.3v. figure 11-2 on page 44 , in system control and reset illustrate s the start-up sequen ce from power-off. 23.4 battery pack short detection the voltage regulator will continuously monitor the operating condition at the vfet terminal. if the voltage at vfet drops below the regulator short-circuit level (rscl), see ?electrical char- acteristics? on page 228 , the voltage regulator enters the battery pack short mode. in this mode, vfet is disconnected from vreg to avoid a quick drop in the voltage regulator output. when the voltage regulator enters this mode, the chip will be completely power ed by the exter- nal reservoir capacitor (creg). this allows the chip to operate a certain time without entering bod reset, even if the vfet voltage is too low for the voltage regulator to operate. an interrupt is issued when the regulator enters battery pack short mode, if the rocwie bit in rocr register is set. this allo ws actions to be taken to reduce power consumption and hence prolonging the time that creg can be used to power the chip. in a typical short-circuit situation, vfet will dr op as a consequence of high current consumption, and recover as soon as the battery protec tion module has disabled the fets. hence creg should be dimensioned so that the chip can su stain operation without entering bod reset, until the fets are disabled either by hw or sw. to minimize power consumption when the vo ltage regulator enters the battery pack short mode, the chip should enter power-save sleep mode as soon as possible after the rocwif interrupt is detected. the watchdog timer should be configured to wake up the cpu after a time that is considered safe, see application note avr132 for use of enhanced watchdog timer. software should then check the status of the roc flag. if the rocs flag is cleared, normal oper- ation may be resumed. 23.5 black-out detection to ensure that the internal logic has safe operating condition, the voltage regulator has built-in black-out detector (blod). if the voltage at the vreg pin drops below the black-out detection level, v blot , the chip will automatically enter power-off mode. 134 8042a?avr?07/09 atmega16hvb/32hvb 23.6 register description 23.6.1 rocr ? regulator operating condition register ? bit 7 - rocs: roc status this bit is set when the voltage regulator operates in the battery pack short mode, and cleared otherwise. ? bit 6:5 - res: reserved bits these bits are reserved bits and will always read as zero. ? bit 4 - rocd: roc disable setting this bit will disable the battery pack short detector and vfet will never be disconnected from the ldo regulator. note that it is not recommended to disable the battery pack short detector by setting the rocd bit unless vfet protection is implemented externally. ? bit 3:2 - res: reserved bits these bits are reserved bits and will always read as zero. ? bit 1 - rocwif: roc warning interrupt flag the rocwif flag is set when the voltage regulator enters the battery pack short mode. the flag is cleared by writing logic one to it or by hardware, by executing the corresponding interrupt handling vector. ? bit 0 - rocwie: roc warning interrupt enable the rocwie bit enables interrupt caused by the regulator operating condition warning inter- rupt flag. bit 76543210 (0xc8) rocs - - rocd - - rocwif rocwie rocr read/write r r r r/w r r r/w r/w initial value00000000 135 8042a?avr?07/09 atmega16hvb/32hvb 24. battery protection 24.1 features ? short-circuit protection ? discharge over-current protection ? charge over-current protection ? discharge high-current protection ? charge high-current protection ? external prot ection input ? programmable and lockable detection levels and reaction times ? autonomous operation independent of cpu 24.2 overview the current battery protection circuitry (cbp) monitors the charge and discharge current and disables c-fet and d-fet if a short-circuit, over -current or high-current condition is detected. there are five different programmable detection levels: short-circuit detection level, discharge over-current detection level, charge over-current detection level, discharge high-current detection level, charge high-current detection level. there are three different programmable delays for activating current battery protection: short-circuit reaction ti me, over-current reac- tion time and high-current reaction time. afte r current battery protection has been activated, the application software must re-enable the fets. the battery protection hardware provides a hold-off time of 1 second before software can re- enable the fets. this provides safety in case the application software should unintentionally try to re-enable the fets too early. the activation of a protection also issues an interrupt to the cpu. the battery protection inter- rupts can be individually enabled and disabled by the cpu. in addition, the module offers an external protecti on input. the activation of the external protec- tion input operates independently of the rest of the battery protection mechanisms. the activation/deactivation of this protection is instantaneously controlled from the external protec- tion input port, and will not deactivate or affe ct the other battery pr otection mechanisms. the effect of the various battery protection types are given in table 24-1 . table 24-1. effect of battery protection types battery protection type interru pt requests pc-fet c-fet d-fet cell balancing fets mcu short-circuit protection entry operational disabled disabled operational operational discharge over-current protection entry operational disabled disabled operational operational charge over-current protection entry operational disabled disabled operational operational discharge high-current protection entry operational disabled disabled operational operational charge high-current protection entry operational disabled disabled operational operational external protection input entry and/or exit oper ational disabled disabled operational operational 136 8042a?avr?07/09 atmega16hvb/32hvb 24.3 operation the current battery protections (cbp) monitors the cell current by sampling the shunt resistor voltage at the ppi/nni input pins. a differential operational amplifier amplifies the voltage with a suitable gain. the output from the operational amplifier is compared to an accurate, programma- ble on-chip voltage reference by an analog comparator. if the shunt resistor voltage is above the detection level for a time longer than the corresponding protection reaction time, the chip activates current protection. a sampled system cl ocked by the internal ulp oscillator is used for short-circuit, over-current, and high-current protection. this ensures a reliable clock source, offset cancellation and low power consumption. 24.3.1 short-circuit protection the short-circuit detection is provided to enable a fast response time to very large discharge currents. if the voltage at the ppi/nni pins is above the short-circuit detection level for a period longer than short-circuit reaction time, the short-circuit protection is activated. when the short-circuit protection is activated, the external d-fet and c-fet are disabled and a current protection timer is started. this time r ensures that the d-fet and c-fet are disabled for at least one second. the application software must then set the dfe and cfe bits in the fet control and status register to re-enable normal operation. if the d-fet is re-enabled before the cause of the short-circuit condition is removed, the short-circuit protection will be activated again. 24.3.2 discharge over-current protection if the voltage at the ppi/nni pins is above the discharge over-current detection level for a time longer than over-current protection reaction time, the chip activates discharge over-current protection. when the discharge over-current protection is activated, the external d-fet and c-fet are disabled and a current protection timer is start ed. this timer ensures that the fets are dis- abled for at least one second. the application software must then set the dfe and cfe bits in the fet control and status register to re-enable normal operation. if the d-fet is re-enabled while the loading of the battery still is too large, the discharge over-current protection will be activated again. 24.3.3 charge over-current protection if the voltage at the ppi/nni pins is above the charge over-current detection level for a time longer than over-current protection reaction time, the chip activates charge over-current protection. when the charge over-current protection is activated, the external d-fet and c-fet are dis- abled and a current protection timer is started. this timer ensures that the fets are disabled for at least one second. the application software must then set the dfe and cfe bits in the fet control and status register to re-enable normal operation. if the c-fet is re-enabled and the charger continues to supply too high currents, the charge over-cur rent protection will be acti- vated again. 24.3.4 discharge high-current protection if the voltage at the ppi/nni pins is above the discharge high-current detection level for a time longer than high-current protection reaction time, the chip activates discharge high-current protection. 137 8042a?avr?07/09 atmega16hvb/32hvb when the discharge high-current protection is activated, the external d-fet and c-fet are dis- abled and a current protection timer is started. this timer ensures that the fets are disabled for at least one second. the application software must then set the dfe and cfe bits in the fet control and status register to re-enable normal operation. if the d-fet is re-enabled while the loading of the battery still is too large, the discharge high-current protection will be activated again. 24.3.5 charge high-current protection if the voltage at the ppi/nni pins is above the charge high-current detection level for a time lon- ger than high-current protection reaction time, the chip activates charge high-current protection. when the charge high-current protection is activated, the external d-fet and c-fet are dis- abled and a current protection timer is started. this timer ensures that the fets are disabled for at least one second. the application software must then set the dfe and cfe bits in the fet control and status register to re-enable normal operation. if the c-fet is re-enabled and the charger continues to supply too high currents, the charge high-cur rent protection will be acti- vated again. the short-circuit, over-curr ent and high-current protection parameters are programmable to adapt to different types of batteries. the parameters are set by writing to i/o registers. the parameter registers can be locked after the initial configuration, prohibiting any further updates until the next hardware reset. refer to ?register description for battery protection? on page 125 for register descriptions. 24.4 external protection input the external protection input uses the alternat e port function of the general purpose high vot- lage i/o to automatically disabling the external charge and discharge-fet. for details, see ?high voltage i/o ports? on page 62 . using this together with the external interrupt (see ?external interrupt characteristics? on page 233 ) features a highly flexible solution for the customer and it allows the user to customize an external protection scheme suitable for battery applications. the external protection input disables both t he c-fet and d-fet immediately when the voltage on extprot pin is pulled high (logic ?1?). it is also used to disable duvr mode if duvr mode is enabled. note that, unlike a battery protection event, the external protection input does not affect the status of the fcsr (cfe, dfe, duvrd, and cps) bits. when the ?high? condition dis- appears, the fet disabling is released immediately. duvr mode is automatically re-entered if previously enabled. the feature is automatically enabled when the chip starts up, and can be disabled before locking the bpcr register. when locking the bpcr register , the external protection feature is also locked. when external protection input is enabled, an override enable si gnal is set to extprot pin configuring the pin as digital input. the port may be set up to give an interrupt when the pin value changes, and the protection status can be read from the port register. note that the external protection input is defaul t enabled. this means that after reset (and dur- ing reset) the port is default overridden to digital input, independent of the port register setting. 138 8042a?avr?07/09 atmega16hvb/32hvb the user must disable the external protection input in the bpcr register before the port can be used as a normal port. also during the reset sequence, the external protection input may disable the fets. conse- quently, if the external protection feature is no t used and duvr mode is enabled in reset, the external protection input must be held low until disabled by sw. it is recommended that the external interrupt on the external protection input port is configured to ?any edge? to generate an interrupt to the mi crocontroller when using this feature, indicating that the fet protection status has changed. by reading the pin register, the external protection status can be determined. if the pin register is set, it means that external protection is trigged and the fet control signals in fcsr (cfe, dfe and duvrd) are overridden and the fets are disabled. in the opposite case, external protection violation is not present. to ensure a safe exit from the external pr otection input condition, the fets and duvr mode should be disabled by sw when an external protection condition is detected. this enables soft- ware to completely control when the fets are switched on again. short pulses on the extprot pin, for instance caused by temporary high voltages on the batt pin when connecting a charger, may trigger the external protection input (refer to ?operating circuit? on page 225 ). however if the sw does not take any action, the c-fet and d-fet will be re-enabled automatically once the external protection condition disappears. figure 24-1. external protection input example. fcsr [cfe] fcsr [dfe] pc0 int0 oc od 139 8042a?avr?07/09 atmega16hvb/32hvb 24.5 optimizing usage for low power consumption in order to reduce power consumption, shor t-circuit, discharge high-current and discharge over-current protection are automatically deact ivated when the d-fet is disabled. the charge over-current and charge high-current protection are disabled when the c-fet is disabled. note however that charge over-current protection and charge high-current protection are never automatically disabled when the chip is operated in duvr mode. also note that none of the current protections are deactivated by the external protection input. to save power during an external protection ev ent, dfe and cfe in the fcsr register should be cleared and make sure that the chip is not operating in duvr mode. 140 8042a?avr?07/09 atmega16hvb/32hvb 24.6 battery protect ion cpu interface the battery protection cpu interface is illustrated in figure 24-2 on page 140 . figure 24-2. battery protection cpu interface each protection originating from the current battery protection module has an interrupt flag. each flag can be read and cleared by the cpu, an d each flag has an individual interrupt enable. all enabled flags are combined into a single battery protection interrupt request to the cpu. this interrupt can wake up the cpu from any operation mode, except power-off. the interrupt flags are cleared by writing a logic ?1? to their bit lo cations from the cpu. an interrupt event for the external protection input can be generated by enabling the external interrupt for the input port. 24.7 register description 24.7.1 bpplr ? battery protection parameter lock register ? bit 7:2 ? res: reserved bits these bits are reserved bits and will always read as zero. ? bit 1 ? bpple: battery protection parameter lock enable ? bit 0 ? bppl: battery protection parameter lock the bpcr, bphctr, bpoctr, bpsctr, bpdhcd, bpchcd, bpdocd, bpcocd and bpscd battery protection regist ers can be locked from any fu rther software updates. once 5 / 5 / 10 / interr u pt re qu est interr u pt ackno w ledge fet control c u rrent battery protection battery protection control register battery protection timing register battery protection le v el register battery protection parameter lock register ppi nn i lock? lock? lock? 8 -bit data bu s po w er-off battery protection interr u pt register c u rrent protection extprot bit 76543210 (0xfe) ??????bpplebpplbpplr read/write rrrrrrr/wr/w initial value00000000 141 8042a?avr?07/09 atmega16hvb/32hvb locked, these registers cannot be accessed until the next hardware reset. this provides a safe method for protecting the registers from unintentional modification by software runaway. it is rec- ommended that software sets these registers shortly after reset, and then protect the registers from further updates. to lock these registers, the following algorithm must be followed: 1. in the same operation, writ e a logic one to bpple and bppl. 2. within the next four clock cycles, in the sa me operation, write a logic zero to bpple and a logic one to bppl. 24.7.2 bpcr ? battery protection control register ? bits 7:6 ? res: reserved bits these bits are reserved bits and will always read as zero. ? bit 5 ? epid: external protection input disable when this bit is set, the external protection i nput is disabled and any external protection input will be ignored. note that this bit overrides the gpio functionality in the external protection input port. if not using the external protection input feature, it is recommended that this bit is always set. ? bit 4 ? scd: short circuit protection disabled when the scd bit is set, the short-circuit protec tion is disabled. the short-circuit detection will be disabled, and any short-circ uit condition will be ignored. ? bit 3 ? docd: discharge over-current protection disabled when the docd bit is set, the discharge over-current protection is disabled. the discharge over-current detection will be disabled, and any discharge ov er-current c ondition will be ignored. ? bit 2 ? cocd: charge over-current protection disable when the cocd bit is set, the charge over-cur rent protection is disabled. the charge over- current detection will be disabl ed, and any charge over-curre nt condition will be ignored. ? bit 1 ? dhcd: discharge high-current protection disabled when the dhcd bit is set, the discharge high-cu rrent protection is di sabled. the discharge high-current detection will be disabled, and any discharge high-current condition will be ignored. ? bit 0 ? chcd: charge high-current protection disable when the chcd bit is set, the charge high-current protection is disabled. the charge high-cur- rent detection will be disa bled, and any charge high-curren t condition will be ignored. note: due to synchronization of parameters between clock domains, a guard time of 3 ulp oscillator cycles + 3 cpu clock cycles is r equired between each time the bpcr register is written. any writ- ing to the bpcr register during this period will be ignored. bit 76543210 (0xfd) ? ? epid scd docd cocd dhcd chcd bpcr read/write r r r/w r/w r/w r/w r/w r/w initial value00000000 142 8042a?avr?07/09 atmega16hvb/32hvb 24.7.3 bpsctr ? battery protection short-current timing register ? bit 7 ? res: reserved bits this bit is reserved in the atmega 16hvb/32hvb and will always read as zero. ? bit 6:0 ? scpt6:0: short-current protection timing these bits control the delay of the short-circuit protection. the short-circuit timing can be set with a step size of 62.5 s as shown in table 24-2 on page 142 . notes: 1. the actual value depends on the actual frequency of the ?ultra low power rc oscillator? on page 27 . see ?electrical characteristics? on page 228 . 2. initial value: scpt[0x10](1ms). 3. an additional delay t d can be expected after enabling the discharge fet due to initialization of the protection circuit. with nomial ulp frequency this delay is maximum 86 s. note: due to synchronization of parameters between clock domains, a guard time of 3 ulp oscillator cycles + 3 cpu clock cycles is re quired between each time the bpsc tr register is written. any writing to the bpsctr register during this period will be ignored. 24.7.4 bpoctr ? battery protection over-current timing register ? bit 7:6 ? res: reserved bits these bits are reserved in the atm ega16hvb/32hvb and will always read as zero. ? bit 5:0 ? ocpt5:0: over-current protection timing these bits control the delay of the over-circuit protection. the over-current timing can be set with a step size of 0.5 ms as shown in table 24-3 on page 143 . bit 76543210 (0xfa) ? scpt[6:0] bpsctr read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 1 0 0 0 0 table 24-2. short-circuit protection reaction time. scpt[6:0] with corresponding short-cir- cuit delay time. short-circuit protection reaction time (1) scpt[6:0] (2) typ 0x00 (15.5 - 70.5 s) + t d (3) 0x01 (15.5 - 70.5 s) + t d (3) 0x02 (78.0 - 133.0 s) + t d (3) 0x03 (140.5 - 195.5 s) + t d (3) ... ... 0x7e (7.83 - 7.88 ms) + t d (3) 0x7f (7.89 - 7.95 ms) + t d (3) bit 76543210 (0xfb) ? ? ocpt[5:0] bpoctr read/write r r r/w r/w r/w r/w r/w r/w initial value00000010 143 8042a?avr?07/09 atmega16hvb/32hvb notes: 1. the actual value depends on the actual frequency of the ?ultra low power rc oscillator? on page 27 . see ?electrical characteristics? on page 228 . 2. initial value. 3. an additional delay t d can be expected after enabling the corresponding fet. this is related to the initialization of the protecti on circuitry. for the discharge over-current protection, this applies when enabling the discharge fet. for charge over-current protection, this applies when enabling the charge fet. with nominal ulp frequency this delay is maximum 0.1 ms. note: due to synchronization of parameters between clock domains, a guard time of 3 ulp oscillator cycles + 3 cpu clock cycles is re quired between each time the bpoc tr register is written. any writing to the bpoctr register during this period will be ignored. 24.7.5 bphctr ? battery protection high-current timing register ? bit 7:6 ? res: reserved bits these bits are reserved in the atm ega16hvb/32hvb and will always read as zero. ? bit 5:0 ? hcpt5:0: high-current protection timing these bits control the delay of the high-circui t protection. the high-current timing can be set with a step size of 2 ms as shown in table 24-4 on page 143 . table 24-3. over-current protection reaction time . ocpt[5:0] with corresponding over-cur- rent delay time. over-current protection reaction time (1) ocpt[5:0] typ 0x00 (0.0 - 0.5 ms) + t d (3) 0x01 (0.0 - 0.5 ms) + t d (3) 0x02 (2) (0.5 - 1.0 ms) + t d (3) 0x03 (1.0 - 1.5 ms) + t d (3) ... ... 0x3e (30.5 - 31.0 ms) + t d (3) 0x3f (31.0 - 31.5 ms) + t d (3) bit 76543210 (0xfc) ? ? hcpt[5:0] bphctr read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 1 table 24-4. high-current protection reaction time. hcpt[5:0] with corresponding high-cur- rent delay time. high-current protection reaction time (1) hcpt[5:0] typ 0x00 (0 - 2 ms) + t d (3) 0x01 (2) (0 - 2 ms) + t d (3) 0x02 (2 - 4 ms) + t d (3) 0x03 (4 - 6 ms) + t d (3) 144 8042a?avr?07/09 atmega16hvb/32hvb notes: 1. the actual value depends on the actual frequency of the ?ultra low power rc oscillator? on page 27 . see ?electrical characteristics? on page 228 . 2. initial value. 3. an additional delay t d can be expected after enabling the corresponding fet. this is related to the initialization of the protecti on circuitry. for the discharge high-current protection, this applies when enabling the discharge fet. for charge high-current protection, this applies when enabling the charge fet. with nominal ulp frequency this delay is maximum 0.2 ms. note: due to synchronization of parameters between clock domains, a guard time of 3 ulp oscillator cycles + 3 cpu clock cycles is re quired between each time the bphc tr register is written. any writing to the bphctr register dur ing this period will be ignored. 24.7.6 bpscd ? battery protection short-circuit detection level register ? bits 7:0 ? scdl7:0: short-circuit detection level these bits sets the r sense voltage level for detection of shor t-circuit in the discharge direction, as defined in table 24-5 on page 145 . note: due to synchronization of parameters between clock domains, a guard time of 3 ulp oscillator cycles + 3 cpu clock cycles is re quired between each time the b pscd register is written. any writing to the bpscd register during this period will be ignored. 24.7.7 bpdocd ? battery protection discharge-over-current detection level register ? bits 7:0 ? docdl7:0: discharge over-current detection level these bits sets the r sense voltage level for detection of discharge over-current, as defined in table 24-5 on page 145 . note: due to synchronization of parameters between clock domains, a guard time of 3 ulp oscillator cycles + 3 cpu clock cycles is re quired between each time the bp docd register is written. any writing to the bpdocd register during this period will be ignored. ... ... 0x3e (122 - 124 ms) + t d (3) 0x3f (124 - 126 ms) + t d (3) table 24-4. high-current protection reaction time. hcpt[5:0] with corresponding high-cur- rent delay time. high-current protection reaction time (1) bit 76543210 (0xf5) scdl[7:0] bpscd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11110011 bit 76543210 (0xf6) docdl[7:0] bpdocd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 0 0 1 1 145 8042a?avr?07/09 atmega16hvb/32hvb 24.7.8 bpcocd ? battery protection charge-over-current detection level register ? bits 7:0 ?cocdl7:0: charge over-current detection level these bits sets the r sense voltage level for detection of charge over-current, as defined in table 24-5 on page 145 . note: due to synchronization of parameters between clock domains, a guard time of 3 ulp oscillator cycles + 3 cpu clock cycles is re quired between each time the bp cocd register is written. any writing to the bpcocd register during this period will be ignored. 24.7.9 bpdhcd ? battery protection discharg e-high-current detection level register ? bits 7:0 ? dhcdl7:0: discharge high-current detection level these bits sets the r sense voltage level for detection of dischargehigh-current, as defined in table 24-5 on page 145 . note: due to synchronization of parameters between clock domains, a guard time of 3 ulp oscillator cycles + 3 cpu clock cycles is re quired between each time the bp dhcd register is written. any writing to the bpdhcd register during this period will be ignored. 24.7.10 bpchcd ? battery protection charge -high-current detect ion level register ? bits 7:0 ?chcdl7:0: charge high-current detection level these bits sets the r sense voltage level for detection of charge high-current, as defined in table 24-5 on page 145 . note: due to synchronization of parameters between clock domains, a guard time of 3 ulp oscillator cycles + 3 cpu clock cycles is re quired between each time the bp chcd register is written. any writing to the bpchcd register during this period will be ignored. bit 76543210 (0xf7) cocdl[7:0] bpcocd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 0 0 1 1 bit 76543210 (0xf8) dhcdl[7:0] bpdhcd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 0 0 1 1 bit 76543210 (0xf9) chcdl[7:0] bpchcd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11110011 table 24-5. dl[7:0] with corresponding r sense voltage levels for all current detection level registers (bpscd, bpdocd, bpcocd, bpdhcd, bpchcd). current protection detection levels dl[7:0] min. typ. (mv) max. 0xf3 20 0xf4 25 0xf5 30 146 8042a?avr?07/09 atmega16hvb/32hvb 24.7.11 bpimsk ? battery protection interrupt mask register ? bit 7:5 ? res: reserved bits these bits are reserved bits and will always read as zero. ? bit 4 ? scie: short-circuit protection activated interrupt the scie bit enables interrupt caused by the short-circuit protection activated interrupt. 0xf6 35 0xf7 40 0xf8 45 0xf9 50 0xfa 55 0xfb 60 0xfc 65 0xfd 70 0x77 80 0x78 90 0x79 100 0x7a 110 0x7b 120 0x7c 130 0x7d 140 0x37 150 0x38 170 0x39 190 0x3a 210 0x3b 230 0x3c 250 0x3d 270 0x17 310 all other values reserved table 24-5. dl[7:0] with corresponding r sense voltage levels for all current detection level registers (bpscd, bpdocd, bpcocd, bpdhcd, bpchcd). current protection detection levels bit 76543210 (0xf2) - - - scie docie cocie dhcie chcie bpimsk read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 147 8042a?avr?07/09 atmega16hvb/32hvb ? bit 3 ? docie: discharge over-current protection activated interrupt the docie bit enables interrupt caused by the discharge over-current protection activated interrupt. ? bit 2 ? cocie: charge over-current protection activated interrupt the cocie bit enables interrupt caused by th e charge over-current protection activated interrupt. ? bit 1 - dhcie : discharger high-current protection activated interrupt the dhcie bit enables interrupt caused by th e discharge high-current protection activated interrupt. ? bit 0 - chcie : charger high-current protection activated interrupt the chcie bit enables interrupt caused by the charge high-current protection activated interrupt. 24.7.12 bpifr ? battery protection interrupt flag register ? bit 7:5 ? res: reserved bit these bits are reserved and will always read as zero. ? bit 4 ? scif: short-circuit protection activated interrupt once short-circuit violation is detected, scif becom es set. the flag is cl eared by writing a logic one to it. ? bit 3 ? docif: discharge over-current protection activated interrupt once discharge over-current violation is detec ted, docif becomes set. the flag is cleared by writing a logic one to it. ? bit 2 ? cocif: charge over-current protection activated interrupt once charge over-current violation is detected, cocif becomes set. the flag is cleared by writing a logic one to it. ? bit 1 ? dhcif: discharge high-current protection activated interrupt once discharge high-current violation is dete cted, dhcif becomes set. the flag is cleared by writing a logic one to it. ? bit 0 ? chcif: charge high-current protection activated interrupt once charge high-current violation is detected, chci f becomes set. the flag is cleared by writ- ing a logic one to it. bit 76543210 (0xf3) - - - scif docif cocif dhcif chcif bpifr read/write r r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 148 8042a?avr?07/09 atmega16hvb/32hvb 25. fet driver 25.1 features ? high side n-channel fet driver for controlling charge and discharge fets in li-ion battery application ? optional deep under-voltage recovery mode allo wing normal operation while charging deeply discharged battery cells from 0-volt without an external pre-charge fet ? optional pre-charge fet mode that allows chargers without pre-charge functionality to charge a deeply discharged battery from 0-volt 25.2 overview the atmega16hvb/32hvb integrates an n-channel fet driver for turning on and off external high-side charge and discharge fets in li-ion battery packs. the fet driver is designed for outputting a high voltage gate overdrive of typically 13v during normal operation. figure 25-1. simplified block diagram. in normal operation fet is controlled by soft ware. sw can enable and disable the charge fet and the discharge fet by writing to the fet control and status register (fcsr). rpc atmega16hvb/32hvb vfet oc od + - batt rdf rcf rbatt pc5 rpf qdf qpf qcf rpvt pvt fet control fet driver duvr_off charge_en discharge_en pwron charger detect optional 2-4 li-ion cells battery pack device / charger 149 8042a?avr?07/09 atmega16hvb/32hvb for safe operation the fet driver automatically turns off both the charge and discharge fet if the autonomous battery protection circuitry (see ?battery protection? on page 135 ) detects an illegal current condition. if such conditions occur, software is not allowed to turn on the fets until the current condition has normalized. to charge deeply discharged cells the atmega16hvb/32hvb can be configured to run in deep under voltage recovery (duvr) mode. using ch argers with pre-charge current functionality, this allows charging of deeply discharge cells without an additional pre-charge fet. for char- gers without a pre-charge limitation current, an optional pre-charge fet in parallel with a charge fet is supported to be able to charge deeply discharge cells. 25.3 operation and usage 25.3.1 normal operation in normal operation (duvrd=1), the fet control is used to enable and disable the charge fet and discharge fet. normally, the fets are enabled and disabled by sw writing to the fet control and status register (f csr). however, the autonomous battery protection circuitry will if necessary override sw settings to protect the bat tery cells from too high charge- or discharge currents. note that the cpu is never allowed to enable a fet that is disabled by the battery pro- tection circuitry. the fet control is shown in figure 25-1 on page 148 . figure 25-2. fet control module. if current protection is activated by the batte ry protection circuitry both the charge-fet and discharge fet will be disabled by hardware. wh en the protection condition disappears the cur- rent protection timer will ensure a hold-off time of 1 second before software can re-enable the external fets. to turn on the charge and discharge fet a minimum vfet supply voltage is required. when the c-fet/d-fet is off with a total cell voltage lower than 6v, sw should not turn on the c- fet/d-fet unless a charger is connected. if the to tal cell voltage is higher than 6v, sw could turn-on the c-fet or d-fet. note however, if the fets are already turned-on, the fet driver can operate in the entire supply operating range of the device. fet control and status register dfe cfe current_protection power-off mode 8-bit data bus charge_en discharge_en duvrd duvr_off current protection timer external_protection_input 150 8042a?avr?07/09 atmega16hvb/32hvb the c-fet/d-fets is switched on by pumping the gate oc/od above the source voltage (pvt/batt) of the external fet. when the gate-source voltage has reached a level higher than typically 13v the pumping frequency is reduced and is regulated to maintain the high gate- source voltage. for low vfet voltages (< 8 volts) this level is never reached, thus the pumping frequency is not reduced. the gate-source voltage for low vfet voltages is close to 2vfet-2v. to avoid over-heating the external fet's when turning them off oc/o d is pulled quickly low. if the c-fet is disabled and d-fet enabled, discharge current will run through the body-drain diode of the c-fet and vice versa. to avoid the potential heat problem from this situation, soft- ware should ensure that the d-fet is not disabled when a large charge current is flowing, and that the c-fet is not disabled when a large discharge current is flowing. 25.3.2 duvr - deep under voltage recovery mode without pre-charge fet to allow charging of deeply discharged cells us ing chargers with pre-charge functionality, the fet driver can be configured to operate in deep under-voltage re covery (duvr) mode. duvr mode allows charging of deeply dischar ged cells without using an additional pre-charge fet. to enter deep under voltage recovery mode, software should clear the duvrd bit (duvrd=0) in the fet control and status register (fcsr). in duvr mode the fet driver regulates the voltage at vfet quickly to typically 4.5v by partly opening the c-fet. at this voltage the chip is fully operational. with the c-fet partly open the charger is allowed to charge the battery with a pre-charge current. as the cell voltage starts to increase above 4.5v the vfet voltage follows the cell voltage. when the total cell voltage has been charged to a voltage higher than 5v, it is safe to exit duvr mode and to turn-on the c-fet completely. software sh ould then set the duvrd bit to exit duvr and fully open the c-fet by setting the cfet bit. note that it is recommended that this is done in two steps. 1. exit duvr mode by setting the duvrd bit. 2. wait until register synchronization is complete (see guard time notice in ?register description? on page 153 ), and enable the c-fet by setting the cfe bit. to avoid potential heating of the c-fet and d-fet in duvr mode, the charger should not be allowed to enter quick-charge until the fet has been completely enabled and the fet driver has exit duvr mode. it is therefore recomm ended to use the cc-adc to continuously monitor the current flowing during duvr mode charging, a nd to turn-off the fets if an illegal charge cur- rent is measured. for fast tracking, it is recommended to use the cc-adc instantaneous current output. for details on cc-adc usage, see ?coulomb counter - dedicated fuel gauging sigma-delta adc? on page 108 . before entering duvr-mode it is recommended to enable the d-fet. after enabling the d-fet it is recommended that sw add a hold-off time of 10ms before duvr mode is entered. this is to make sure that the d-fe t is completely enabled. to avoid that the charger enters quick-charge before the battery has exit duvr mode, it is rec- ommended that either 1. the battery controls when the charger is allowed to enter quick-charge. this is done by communicating to the charger over the smbus line when the charger is allowed to enter increase the charge current. 2. the charger itself controls when to enter quick-charge by sensing the voltage at the pack+ terminal. it is not recommended that the charger allows quick-charge until the charger senses a pack+ voltage higher than 7v. to avoid potential heating problem sw need to ensure to exit duvr mode and enable the c-fet before the charger sees this limit. 151 8042a?avr?07/09 atmega16hvb/32hvb when the battery is started from a power-off condition by connecting a legal charger, sw should determine whether to allow charging or not before enabling the c-fet. before allowing charging it is recommended to use the v-adc to measure the cell temperature and cell voltages. depend- ing on the total cell voltage, the device should either start up in duvr mode or in normal charging mode with the c-fet and d-fet enabled. ? if the total cell voltage is below 4.5v, the ba ttery should enter duvr charging mode. this ensures safe operation voltage while allowing charging. ? if the total cell voltage is above 4.5v, the battery should enter normal charging mode with both c-fet and d-fet enabled. the ?duvr mode charging in 3-cell mode configuration? on page 151 shows an example of charging 3 deeply discharged li-ion cells in series using duvr mode. figure 25-3. duvr mode charging in 3-cell mode configuration 1. a charger with 12.6v charge voltage is plugged to the pack+ pin and the atmega16hvb/32hvb enters reset mode. charger should be configured with a charge current limit (pre-charge current). 2. the atmega16hvb/32hvb exit reset and initializes modules. to determine if charging should be allowed and if duvr mode should be entered, cell temperature and cell volt- ages are measured by the v-adc. 3. d-fet is enabled and the vfet voltage increase to the pack+ level. 4. duvr mode is entered by clearing the duvrd bit in fcsr. the vfet voltage and the pack+ voltage will now be regula ted to approximately 4.5v. 5. the total cell voltage has reached the regu lated vfet limit and vfet follows the cell voltage as the battery is charged. 6. the total cell voltage has reached 5v. duvr mode is disabled and the c-fet can be fully enabled. duvr mode should be disabled before the c-cfet is enabled. vfet and 1 2 3 4 5 6 7 0 2 4 6 8 10 12 14 v oltage reset du v rd cfe dfe p v t v fet pa c k+ 152 8042a?avr?07/09 atmega16hvb/32hvb pack+ will therefore rise to the charger volta ge for a short period before the c-fet is enabled. 7. battery voltage reached charger voltage. 25.3.3 deep under voltage operation with pre-charge fet if a charger without pre- charge functionality is used, the pre-charge fe t will provide the current path and the pre-charge resistor will limit the char ge current during chargi ng of deeply over-dis- charged cells. after reaching sufficient battery voltage it is safe to turn on the charge fet to increase the charge current. deep under voltage operation with pre-charge fet is supported through pc5, which is a high voltage open drain pin. for configuration and usage of this pin, see ?high voltage i/o ports? on page 62 . 25.3.4 operation in reset and power off in reset and power-off the c-fet and d-fet will be automatically tu rned off. safety is remained by active pulling oc/o d hard to ground. 153 8042a?avr?07/09 atmega16hvb/32hvb 25.4 register description 25.4.1 fcsr ? fet control and status register ? bits 7:4 ? res: reserved bits these bits are reserved bits in the atmega 16hvb/32hvb, and will always read as zero. ? bit 3 ? duvrd: deep under-voltage recovery disabled when the duvrd is cleared (zero), the fet driv er will be forced to operate in deep under-volt- age recovery duvr mode. see ?duvr - deep under voltage recovery mode without pre- charge fet? on page 150 for details. to avoid that the fet driver tries to switch on the c-fet during current protection or during internal reset, the duvrd bit is overridden to one by hard- ware in these cases. when this bit is set (one), deep under-voltage recovery mode of the fet driver will be disabled. ? bit 2 ? cps: current protection status the cps bit shows the status of the current protection. this bit is set (one) when a current pro- tection is active, and cleared (zero) otherwise. ? bit 1 ? dfe: discharge fet enable when the dfe bit is cleared (z ero), the discharge fet will be dis abled regardless of the state of the battery protection circuitry. when this bit is set (one), the discharge fet is enabled. this bit will automatically be cleared by the cbp circuitry when current protection is activated. when this bit is cleared, short-circuit, discharge hi gh-current and discharge over-current are disabled regardless of the settings in the bpcr register. ? bit 0 ? cfe: charge fet enable when the cfe bit is cleared (zero), the charge fet will be disabled re gardless of the state of the battery protection circuitry. when this bit is set (one), the charge fet is enabled. this bit will automatically be cleared by the cbp circuitry when current protection is activated. when this bit is cleared and the duvrd bit is set, charge high-current protection and charge over- current protection are disabled regardless of th e settings in the bpcr register. when the duvrd bit is cleared, the charge fet will be enabled by duvr mode regardless of the cfe status. notes: 1. due to synchronization of parameters between clock domains, a guard time of 3 ulp oscillator cycles + 3 cpu clock cycles is r equired between each time the fc sr register is written. any writing to the fcsr register during this period will be ignored. 2. the nfet drivers require a minimum total cell voltage of 6v or higher or a charger connected to turn-on the fets. note that this limit only applies if the fet is disabled in advanced. if the fet is already enabled, the fet will be full y operational in the entire voltage range of the device (4-25v). bit 7 6 5 4 3 2 1 0 (0xf0) ? ? ? ? duvrd cps dfe cfe fcsr read/write r r r r r/w r r/w r/w initial value 0 0 0 0 1 0 0 0 154 8042a?avr?07/09 atmega16hvb/32hvb 26. cell balancing 26.1 overview atmega16hvb/32hvb incorporates cell balancing fets. the chip provides one cell balancing fet for each battery cell in series. the fets are directly controlled by the application software, allowing the cell balancing algorithms to be implemented in software. the fets are connected in parallel with the individua l battery cells. the cell bal ancing is illustrated in figure 26-1 . the fig- ure shows a four-cell configuration. the cell balancing fets are disabled in the power-off mode. for typical current through the cell balancing fets, see ?electrical characteristics? on page 228 . the cell balancing fets are controlled by the cbcr. neighbouring fets cannot be simultane- ously enabled. if trying to enable two neighbouring fets , both will be disabled. figure 26-1. cell balancing cell balancing control register t cb rp rp rp rp t cb t cb t cb level shift level shift level shift level shift pv1 nv pv2 pv3 pv4 8-bit data bus rp 155 8042a?avr?07/09 atmega16hvb/32hvb 26.2 register description 26.2.1 cbcr ? cell balancing control register ? bit 7:4 ? res: reserved bits these bits are reserved bits in the atme ga16hvb/32hvb and will always read as zero. ? bit 3 ? cbe4: cell balancing enable 4 when this bit is set, the integrated cell ba lancing fet between terminals pv4 and pv3 will be enabled. when the bit is cleared, the cell bala ncing fet will be disabled. the cell balancing fets are always disabled in power-off mode. cbe4 cannot be set if cbe3 is set. ? bit 2 ? cbe3: cell balancing enable 3 when this bit is set, the integrated cell ba lancing fet between terminals pv3 and pv2 will be enabled. when the bit is cleared, the cell bala ncing fet will be disabled. the cell balancing fets are always disabled in power-off mode. cbe3 cannot be set if cbe2 or cbe4 is set. ? bit 1 ? cbe2: cell balancing enable 2 when this bit is set, the integrated cell ba lancing fet between terminals pv2 and pv1 will be enabled. when the bit is cleared, the cell bala ncing fet will be disabled. the cell balancing fets are always disabled in power-off mode. cbe2 cannot be set if cbe1 or cbe3 is set. ? bit 0 ? cbe1: cell balancing enable 1 when this bit is set (one), t he integrated cell balancing fet between terminals pv1 and nv will be enabled. when the bit is cleared (zero), th e cell balancing fet will be disabled. the cell bal- ancing fets are always disabled in power-off mode. cbe1 cannot be set if cbe2 is set. bit 76543210 (0xf1) ? ? ? ? cbe4 cbe3 cbe2 cbe1 cbcr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 156 8042a?avr?07/09 atmega16hvb/32hvb 27. 2-wire serial interface 27.1 features ? simple yet powerful and flexible communication interface, only two bus lines needed ? both master and sla ve operation supported ? device can operate as transmitter or receiver ? 7-bit address space allows up to 128 different slave addresses ? multi-master arbitration support ? supports sm bus transfer speeds from 10 to 100khz ? slew-rate limited output drivers ? noise suppression circuitry rejects spikes on bus lines ? fully programmable slave address with general call support ? address recognition causes wake-up when avr is in sleep mode 27.2 two-wire serial interface bus definition the two-wire serial interface (twi) is ideally suited for typical microcontroller applications. the twi protocol allows the systems designer to in terconnect up to 128 diffe rent devices using only two bi-directional bus lines, one for clock (scl) and one for data (sda). the only external hard- ware needed to implement the bus is a single pull- up resistor for each of the twi bus lines. all devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the twi protocol. when the twi is not used, power consumption can be minimized by writing the prtwi bit in prr0 to one. see ?prr0 ? power reduction register 0? on page 40 for details on how to use the prtwi bit. figure 27-1. twi bus interconnection device 1 device 2 device 3 device n sda scl ........ r1 r2 v bus 157 8042a?avr?07/09 atmega16hvb/32hvb 27.2.1 twi terminology the following definitions are frequently encountered in this section. 27.2.2 electrical interconnection as depicted in figure 27-1 , both bus lines are connected to the positive supply voltage through pull-up resistors. the bus drivers of all twi-compliant devices are open-drain or open-collector. this implements a wired-and functi on which is essential to the operation of the interface. a low level on a twi bus line is generated when one or more twi devices output a zero. a high level is output when all twi devices tri-state their outputs, allowing the pull-up resistors to pull the line high. note that all avr devices connected to the twi bus must be powered in order to allow any bus operation. the number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400 pf and the 7-bit slave address space. a detailed specification of the electrical char- acteristics of the twi is given in ?2-wire serial interface characteristics? on page 235 . 27.3 data transfer and frame format 27.3.1 transferring bits each data bit transferred on the twi bus is accompanied by a pulse on the clock line. the level of the data line must be stable when the clock line is high. the only exception to this rule is for generating start and stop conditions. figure 27-2. data validity table 27-1. twi terminology term description master the device that initiates and terminates a transmission. the master also generates the scl clock. slave the device addressed by a master. transmitter the device placing data on the bus. receiver the device reading data from the bus. sda scl data stable data stable data change 158 8042a?avr?07/09 atmega16hvb/32hvb 27.3.2 start and stop conditions the master initiates and terminates a data transmi ssion. the transmission is initiated when the master issues a start condition on the bus, and it is terminated when the master issues a stop condition. between a start and a stop condition, the bus is considered busy, and no other master should try to seize control of the bus. a special case occurs when a new start condition is issued between a start and stop condition. this is referred to as a repeated start condition, and is used when the master wis hes to initiate a new transfer without relin- quishing control of the bus. after a repeated start, the bus is considered busy until the next stop. this is identical to the start behavior, and therefore start is used to describe both start and repeated start for the remainder of this datasheet, unless otherwise noted. as depicted below, start and stop conditions are signalled by changing the level of the sda line when the scl line is high. figure 27-3. start, repeated start, and stop conditions 27.3.3 address packet format all address packets transmitted on the twi bus are nine bits long , consisting of seven address bits, one read/write control bit and an acknowledge bit. if the read/write bit is set, a read operation is to be performed, otherwise a write operation should be performed. when a slave recognizes that it is being a ddressed, it should acknowledge by pulling sda low in the ninth scl (ack) cycle. if the addressed slave is busy, or for some other reason can not service the mas- ter?s request, the sda line should be left high in the ack clock cycle. the master can then transmit a stop condition, or a repeated start condition to initiate a new transmission. an address packet consisting of a slave address and a read or a write bit is called sla+r or sla+w, respectively. the msb of the address byte is transmitted first. slave addresses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call. when a general call is issued, all slaves should respond by pulling the sda line low in the ack cycle. a general call is used when a master wi shes to transmit the same message to several slaves in the system. when the general call address followed by a write bit is transmitted on the bus, all slaves set up to ackn owledge the general call will pull th e sda line low in the ack cycle. the following data packets will then be received by all the slaves that acknowle dged the general call. note that transmitting the general call add ress followed by a read bit is meaningless, as this would cause contention if several slaves started transmitting different data. all addresses of the format 1111 xxx should be reserved for future purposes. sda scl start stop repeated start stop start 159 8042a?avr?07/09 atmega16hvb/32hvb figure 27-4. address packet format 27.3.4 data packet format all data packets transmitted on the twi bus are nine bits long, consisting of one data byte and an acknowledge bit. during a data transfer, the master generates the clock and the start and stop conditions, while the receiver is res ponsible for acknowledging the reception. an acknowledge (ack) is signalled by the receiver pulling the sda line low during the ninth scl cycle. if the receiver leaves the sda line high, a nack is signalled. when the receiver has received the last byte, or for some reason cannot receive any more bytes, it should inform the transmitter by sending a nack after the final byte. the msb of the data byte is transmitted first. figure 27-5. data packet format 27.3.5 combining address and data packets into a transmission a transmission basically consists of a start co ndition, a sla+r/w, one or more data packets and a stop condition. an empty message, consisting of a start followed by a stop condi- tion, is illegal. note that the wired-anding of the scl line can be used to implement handshaking between the master and the slave. the slave can extend the scl low period by pulling the scl line low. this is useful if the cloc k speed set up by the master is too fast for the slave, or the slave needs extra time for proces sing between the data transmissions. the slave extending the scl low period will not affect t he scl high period, which is determined by the master. as a consequence, the slave can reduce the twi data transfer speed by prolonging the scl duty cycle. figure 27-6 shows a typical data transmission. note that several data bytes can be transmitted between the sla+r/w and the stop condition, depending on the software protocol imple- mented by the application software. sda scl start 12 789 addr msb addr lsb r/w ack 12 789 data msb data lsb ack aggregate sda sda from transmitter sda from receiver scl from master sla+r/w data byte stop, repeated start, or next data byte 160 8042a?avr?07/09 atmega16hvb/32hvb figure 27-6. typical data transmission 27.4 multi-master bus systems, arbitration and synchronization the twi protocol allows bus systems with seve ral masters. special concerns have been taken in order to ensure that transmis sions will proceed as normal, even if two or more masters initiate a transmission at the same time. two problems arise in multi-master systems: ? an algorithm must be implemented allowing only one of the masters to complete the transmission. all other masters should cease transmission when they discover that they have lost the selection process. this selection proc ess is called arbitration. when a contending master discovers that it has lost the arbitration process, it should immediately switch to slave mode to check whether it is being addressed by the winning master. the fact that multiple masters have started transmission at the same time should not be detectable to the slaves (i.e., the data being transferred on the bus must not be corrupted). ? different masters may use different scl frequencies. a scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. this will fac ilitate the arbitration process. the wired-anding of the bus lines is used to solv e both these problems. the serial clocks from all masters will be wired-anded, yielding a co mbined clock with a high period equal to the one from the master with the shortest high period. the low period of the combined clock is equal to the low period of the master with the longest low period. note that all masters listen to the scl line, effectively starting to count their scl high and low time-out periods when the combined scl line goes high or low, respectively. figure 27-7. scl synchronization between multiple masters 12 789 data byte data msb data lsb ack sda scl start 12 789 addr msb addr lsb r/w ack sla+r/w stop ta low ta high scl from master a scl from master b scl bus line tb low tb high masters start countin g low period masters start countin g hi g h period 161 8042a?avr?07/09 atmega16hvb/32hvb arbitration is carried out by all masters cont inuously monitoring the sda line after outputting data. if the value read from the sda line does not match the value the master had output, it has lost the arbitration. note that a master can only lose arbitration when it outputs a high sda value while another master outputs a low value. the losing master should immediately go to slave mode, checking if it is being addressed by the winning master. the sda line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or address packet. arbitration will cont inue until only one master re mains, and this may take many bits. if several masters are trying to address the same slave, ar bitration will cont inue into the data packet. figure 27-8. arbitration between two masters note that arbitration is not allowed between: ? a repeated start cond ition and a data bit. ? a stop condition and a data bit. ? a repeated start and a stop condition. it is the user software?s responsibility to ensur e that these illegal arbitration conditions never occur. this implies that in multi-master systems, all data transfers must use the same composi- tion of sla+r/w and data packets. in other words: all transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. sda from master a sda from master b sda line synchronized scl line start master a loses arbitration, sda a sda 162 8042a?avr?07/09 atmega16hvb/32hvb 27.5 overview of the twi module the twi module is comprised of several submodules, as shown in figure 27-9 . the shaded reg- isters are accessible through the avr data bus. figure 27-9. overview of the twi module 27.5.1 scl and sda pins these pins interface the avr twi with the rest of the mcu system. the output drivers contain a slew-rate limiter in order to conform to the twi specification. the input stages contain a spike suppression unit removing spikes shorter than 50 ns. twi unit address register (twar) address match unit address comparator control unit status register (twsr) state machine and status control scl slew-rate control spike filter sda slew-rate control spike filter bit rate generator bit rate register (twbr) prescaler bus interface unit start / stop control arbitration detection ack spike suppression address/data shift register (twdr) control register (twcr) 163 8042a?avr?07/09 atmega16hvb/32hvb 27.5.2 bit rate generator unit this unit controls the period of scl when oper ating in a master mode. the scl period is con- trolled by settings in the twi bit rate register (twbr) and the prescaler bits in the twi status register (twsr). slave operation does not depend on bit rate or prescaler settings, but the cpu clock frequency in the slave must be at least 16 times higher than the scl frequency. note that slaves may prolong the scl low period, thereby reducing the average twi bus clock period. the scl frequency is generated according to the following equation: ? twbr = value of the twi bit rate register. ? twps = value of the prescaler bits in the twi status register. note: the twi clock is synchronous to the cpu. 27.5.3 bus interface unit this unit contains the data and address shif t register (twdr), a start/stop controller and arbitration detection hardware. the twdr contains the address or data bytes to be transmitted, or the address or data bytes received. in addition to the 8-bit twdr, the bus interface unit also contains a register containing the (n)ack bit to be transmitted or receiv ed. this (n)ack regis- ter is not directly accessible by the application software. however, when re ceiving, it can be set or cleared by manipulating the twi control r egister (twcr). when in transmitter mode, the value of the received (n)ack bit can be determined by the value in the twsr. the start/stop controller is responsible for gene ration and detection of start, repeated start, and stop conditions. the start/stop controller is able to detect start and stop conditions even when the avr mcu is in one of the sleep modes, enabling the mcu to wake up if addressed by a master. if the twi has initiated a transmission as master, the arbitration detection hardware continu- ously monitors the transmission trying to determine if arbitration is in process. if the twi has lost an arbitration, the control unit is informed. correct action can then be taken and appropriate status codes generated. 27.5.4 address match unit the address match unit checks if received address bytes match the 7-bit address in the twi address register (twar). if the twi general call recognition enable (twgce) bit in the twar is written to one, all incoming address bits will also be compared against the general call address. upon an address match, the control unit is informed, allowing correct action to be taken. the twi may or may not acknowledge it s address, depending on settings in the twcr. the address match unit is able to compare addresses even when the avr mcu is in sleep mode, enabling the mcu to wake-up if addressed by a master. scl frequency twi clock frequency 16 2(twbr) 4 twps ? + ----------------------------------------------------------- = 164 8042a?avr?07/09 atmega16hvb/32hvb 27.5.5 control unit the control unit monitors the twi bus and generates responses corresponding to settings in the twi control register (twcr). when an event requiring the attention of the application occurs on the twi bus, the twi interrupt flag (twint) is asserted. in the next clock cycle, the twi sta- tus register (twsr) is updated with a stat us code identifying the event. the twsr only contains relevant status information when the twi interrupt flag is asserted. at all other times, the twsr contains a special stat us code indicating that no relevant status information is avail- able. as long as the twint flag is set, the scl line is held low. this allows the application software to complete its tasks before allowing the twi transmission to continue. the twint flag is set in the following situations: ? after the twi has transmitted a start/repeated start condition. ? after the twi has transmitted sla+r/w. ? after the twi has transmitted an address byte. ? after the twi has lost arbitration. ? after the twi has been addressed by own slave address or general call. ? after the twi has received a data byte. ? after a stop or repeated start has been received while still addressed as a slave. ? when a bus error has occurred due to an illegal start or stop condition. 165 8042a?avr?07/09 atmega16hvb/32hvb 27.6 using the twi the avr twi is byte-oriented and interrupt based. interrupts are issued after all bus events, like reception of a byte or transmission of a start condition. because the twi is interrupt-based, the application software is free to carry on other operations during a twi byte transfer. note that the twi interrupt enable (twie) bit in twcr to gether with the global interrupt enable bit in sreg allow the application to decide whether or not assertion of the twint flag should gener- ate an interrupt request. if the twie bit is cl eared, the application must poll the twint flag in order to detect actions on the twi bus. when the twint flag is asserted, the twi has finished an operation and awaits application response. in this case, the twi status register (twsr) contains a value indicating the current state of the twi bus. the application software can then decide how the twi should behave in the next twi bus cycle by manipulating the twcr and twdr registers. figure 27-10 is a simple example of how the application can interface to the twi hardware. in this example, a master wishes to transmit a single data byte to a slave. this description is quite abstract, a more detailed explanation follows later in this section. a simple code example imple- menting the desired behavior is also presented. figure 27-10. interfacing the application to the twi in a typical transmission 1. the first step in a twi transmission is to transmit a start condition. this is done by writing a specific value into twcr, instructing the twi hardware to transmit a start condition. which value to write is described later on. however, it is important that the twint bit is set in the value written. writin g a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. immediately after the application has cleared twint, the twi will in itiate transmission of the start condition. 2. when the start condition has been transmitted, the twint flag in twcr is set, and twsr is updated with a status code indicating that the start condition has success- fully been sent. 3. the application software should now examine the value of twsr, to make sure that the start condition was successfully transmitted. if twsr indicates otherwise, the applica- tion software might take some s pecial action, like calling an er ror routine. assuming that the status code is as expected, the application must load sla+w into twdr. remember start sla+w a data a stop 1. application writes to twcr to initiate transmission of start 2. twint set. status code indicates start condition sent 4. twint set. status code indicates sla+w sent, ack received 6. twint set. status code indicates data sent, ack received 3. check twsr to see if start was sent. application loads sla+w into twdr, and loads appropriate control signals into twcr, making sure that twint is written to one 5. check twsr to see if sla+w was sent and ack received. application loads data into twdr, and loads appropriate control signals into twcr, making sure that twint is written to one 7. check twsr to see if data was sent and ack received. application loads appropriate control signals to send stop into twcr, making sure that twint is written to one twi bus indicates twint set application action twi hardware action 166 8042a?avr?07/09 atmega16hvb/32hvb that twdr is used both for address and data. after twdr has been loaded with the desired sla+w, a specific value must be written to twcr, instructing the twi hardware to transmit the sla+w present in twdr. whic h value to write is described later on. however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. immediately afte r the application has cleared twint, the twi will initiate transmission of the address packet. 4. when the address packet has been transmitted, the twint flag in twcr is set, and twsr is updated with a status code indicati ng that the address packet has successfully been sent. the status code will also reflect whether a slav e acknowledged the packet or not. 5. the application software should now examine the value of twsr, to make sure that the address packet was successfully transmitted, and that the value of the ack bit was as expected. if twsr indicates otherwise, the application software might take some special action, like calling an error rout ine. assuming that the stat us code is as expected, the application must load a data packet into twdr. subsequently, a specific value must be written to twcr, instructing the twi hardware to transmit the data packet present in twdr. which value to write is described late r on. however, it is important that the twint bit is set in the value written. writin g a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. immediately after the application has cleared twint, the twi will initiate transmission of the data packet. 6. when the data packet has been transmitted, the twint flag in twcr is set, and twsr is updated with a status code indicating that the data packet has successfully been sent. the status code will also reflect whether a slave acknowledged the packet or not. 7. the application software should now examine the value of twsr, to make sure that the data packet was successfully transmitted, and that the value of the ack bit was as expected. if twsr indicates otherwise, the application software might take some special action, like calling an error rout ine. assuming that the stat us code is as expected, the application must write a specific value to tw cr, instructing the twi hardware to transmit a stop condition. which value to write is described later on. however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the tw int bit in twcr is set. immediately after the application has cleared twint, the twi w ill initiate transmission of the stop condi- tion. note that twint is not set after a stop condition has been sent. even though this example is simple, it shows t he principles involved in all twi transmissions. these can be summarized as follows: ? when the twi has finished an operation and expects application response, the twint flag is set. the scl line is pulled low until twint is cleared. ? when the twint flag is set, the user must update all twi registers with the value relevant for the next twi bus cycle. as an example, twdr must be loaded with the value to be transmitted in the next bus cycle. ? after all twi register updates and other pending application software tasks have been completed, twcr is written. when writing twcr, the twint bit should be set. writing a one to twint clears the flag. t he twi will then commence execut ing whatever operation was specified by the twcr setting. in the following an assembly and c implementation of the example is given. note that the code below assumes that several definitions have been made for example by using include-files. 167 8042a?avr?07/09 atmega16hvb/32hvb note: 1. see ?about code examples? on page 8 . assembly code example (1) c example (1) comments 1 ldi r16, (1< 169 8042a?avr?07/09 atmega16hvb/32hvb figure 27-11. data transfer in master transmitter mode a start condition is sent by wr iting the following value to twcr: twen must be set to enable the two-wire serial interface, twsta must be written to one to transmit a start condition and twint must be written to one to clear the twint flag. the twi will then test the two-wire serial bus and gene rate a start condition as soon as the bus becomes free. after a start condition has been transmitted, the twint flag is set by hard- ware, and the status code in twsr will be 0x08 (see table 27-2 ). in order to enter mt mode, sla+w must be transmitted. this is done by writing sla+w to twdr. thereafter the twint bit should be cleared (by writing it to one) to continue the transfer. this is accomplished by writing the following value to twcr: when sla+w have been transmitted and an acknowledgment bit has been received, twint is set again and a number of status codes in twsr are possible. possible status codes in master mode are 0x18, 0x20, or 0x38. the appropriate action to be taken for each of these status codes is detailed in table 27-2 . when sla+w has been successfully transmitted, a data packet should be transmitted. this is done by writing the data byte to twdr. twdr must only be written when twint is high. if not, the access will be discarded, and the write collision bit (twwc) will be set in the twcr regis- ter. after updating twdr, the twint bit should be cleared (by writing it to one) to continue the transfer. this is acco mplished by writing the following value to twcr: this scheme is repeated until the last byte has been sent and the transfer is ended by generat- ing a stop condition or a repeated start condition. a stop condition is generated by writing the following value to twcr: twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x device 1 master transmitter device 2 slave receiver device 3 device n sda scl ........ r1 r2 v bus 170 8042a?avr?07/09 atmega16hvb/32hvb a repeated start condition is generated by writing the following value to twcr: after a repeated start condition (state 0x10) the two-wire serial interface can access the same slave again, or a new slave without transmitting a stop condition. repeated start enables the master to switch between slaves, master transmitter mode and master receiver mode without losing control of the bus. twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x table 27-2. status codes for master transmitter mode status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial inter- face hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x08 a start condition has been transmitted load sla+w x 0 1 x sla+w will be transmitted; ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+w or load sla+r x x 0 0 1 1 x x sla+w will be transmitted; ack or not ack will be received sla+r will be transmitted; logic will switch to master receiver mode 0x18 sla+w has been transmitted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x20 sla+w has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x28 data byte has been transmit- ted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x30 data byte has been transmit- ted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x38 arbitration lost in sla+w or data bytes no twdr action or no twdr action 0 1 0 0 1 1 x x two-wire serial bus will be released and not ad- dressed slave mode entered a start condition will be transmitted when the bus becomes free 171 8042a?avr?07/09 atmega16hvb/32hvb figure 27-12. formats and states in the master transmitter mode s sla w a data a p $08 $18 $28 r sla w $10 ap $20 p $30 a or a $38 a other master continues a or a $38 other master continues r a $68 other master continues $78 $b0 to corresponding states in slave mode mt mr successfull transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the p rescaler bits are zero or masked to zero s 172 8042a?avr?07/09 atmega16hvb/32hvb 27.7.2 master receiver mode in the master receiver mode, a number of data bytes are received from a slave transmitter (see figure 27-13 ). in order to enter a master mode, a start condition must be transmitted. the for- mat of the following address packet determines whether master transmitter or master receiver mode is to be entered. if sla+w is transmitte d, mt mode is entered, if sla+r is transmitted, mr mode is entered. all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. figure 27-13. data transfer in ma ster receiver mode a start condition is sent by wr iting the following value to twcr: twen must be written to one to enable the two-wire serial interface, twsta must be written to one to transmit a start condit ion and twint must be set to clear the twint flag. the twi will then test the two-wire serial bus and generate a start condition as soon as the bus becomes free. after a start condition has been transmitted, the twint flag is set by hardware, and the status code in twsr will be 0x08 (see table 27-2 on page 170 ). in order to enter mr mode, sla+r must be transmitted. this is done by wr iting sla+r to twdr. th ereafter the twint bit should be cleared (by writing it to one) to continue the transfer. this is accomplished by writing the following value to twcr: when sla+r have been transmitted and an acknow ledgment bit has been received, twint is set again and a number of status codes in twsr are possible. possible status codes in master mode are 0x38, 0x40, or 0x48. the appropriate action to be taken for each of these status codes is detailed in table 27-12 on page 171 . received data can be read from the twdr register when the twint flag is set high by hardware. th is scheme is repeated until the last byte has been received. after the last byte has been received, the mr should inform the st by sending a nack after the last received data byte. the transfer is ended by generating a stop condition or a repeated start condition. a stop condition is generated by writing the following value to twcr: twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x device 1 master receiver device 2 slave transmitter device 3 device n sda scl ........ r1 r2 v bus 173 8042a?avr?07/09 atmega16hvb/32hvb a repeated start condition is generated by writing the following value to twcr: after a repeated start condition (state 0x10) the two-wire serial interface can access the same slave again, or a new slave without transmitting a stop condition. repeated start enables the master to switch between slaves, master transmitter mode and master receiver mode without losing control over the bus. twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x table 27-3. status codes for master receiver mode status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial inter- face hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x08 a start condition has been transmitted load sla+r x 0 1 x sla+r will be transmitted ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+r or load sla+w x x 0 0 1 1 x x sla+r will be transmitted ack or not ack will be received sla+w will be transmitted logic will switch to master transmitter mode 0x38 arbitration lost in sla+r or not ack bit no twdr action or no twdr action 0 1 0 0 1 1 x x two-wire serial bus will be released and not ad- dressed slave mode will be entered a start condition will be transmitted when the bus becomes free 0x40 sla+r has been transmitted; ack has been received no twdr action or no twdr action 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x48 sla+r has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x50 data byte has been received; ack has been returned read data byte or read data byte 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x58 data byte has been received; not ack has been returned read data byte or read data byte or read data byte 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 174 8042a?avr?07/09 atmega16hvb/32hvb figure 27-14. formats and states in the master receiver mode 27.7.3 slave receiver mode in the slave receiver mode, a number of data bytes are received from a master transmitter (see figure 27-15 ). all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. figure 27-15. data transfer in slave receiver mode to initiate the slave receiver mode, twar and twcr must be initialized as follows: s sla r a data a $08 $40 $50 sla r $10 ap $48 a or a $38 other master continues $38 other master continues w a $68 other master continues $78 $b0 to corresponding states in slave mode mr mt successfull reception from a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the p rescaler bits are zero or masked to zero p data a $58 a r s device 3 device n sda scl ........ r1 r2 v bus device 2 master transmitter device 1 slave receiver 175 8042a?avr?07/09 atmega16hvb/32hvb the upper seven bits are the address to which t he two-wire serial interface will respond when addressed by a master. if the lsb is set, the twi will respond to the general call address (0x00), otherwise it will ignore the general call address. twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledgment of the device?s own slave add ress or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. if the direction bit is ?0? (write), the twi will operate in sr mode, otherwise st mode is entered. after its own slave address and the write bit have been received, the twint flag is set and a valid status code can be read from twsr. the status c ode is used to determine the appropriate soft- ware action. the appropriate action to be taken for each status code is detailed in table 27-4 . the slave receiver mode may also be entered if arbitration is lost while the twi is in the master mode (see states 0x68 and 0x78). if the twea bit is reset during a transfer, the tw i will return a ?not acknowledge? (?1?) to sda after the next received data byte. this can be us ed to indicate that the slave is not able to receive any more bytes. while twea is zero, the twi does not acknowledge its own slave address. however, the two-wire serial bus is still monitored and address recognition may resume at any time by setting twea. this implies that the twea bit may be used to temporarily isolate the twi from the two-wire serial bus. in all sleep modes other than idle mode, the clock system to the twi is turned off. if the twea bit is set, the interface can still acknowledge its own slave ad dress or the general call address by using the two-wire serial bus clock as a clock source. the part will then wake-up from sleep and the twi will hold the scl clock low during the wake up and until the twint flag is cleared (by writing it to one). further data reception will be carri ed out as normal, with the avr clocks running as normal. observe that if the avr is set up with a long start-up time, the scl line may be held low for a long time, blocking other data transmissions. note that the two-wire serial interface data register ? twdr does not reflect the last byte present on the bus when waking up from these sleep modes. twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x 176 8042a?avr?07/09 atmega16hvb/32hvb table 27-4. status codes for slave receiver mode status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x60 own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x68 arbitration lost in sla+r/w as master; own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x70 general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x78 arbitration lost in sla+r/w as master; general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x80 previously addressed with own sla+w; data has been received; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x88 previously addressed with own sla+w; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0x90 previously addressed with general call; data has been re- ceived; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x98 previously addressed with general call; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xa0 a stop condition or repeated start condition has been received while still addressed as slave read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 177 8042a?avr?07/09 atmega16hvb/32hvb figure 27-16. formats and states in the slave receiver mode s sla w a data a $60 $80 $88 a $68 reception of the own slave address and one or more data bytes. all are acknowledged last data byte received is not acknowledged arbitration lost as master and addressed as slave reception of the general call address and one or more data bytes last data byte received is not acknowledged n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p or s data a $80 $a0 p or s a a data a $70 $90 $98 a $78 p or s data a $90 $a0 p or s a general call arbitration lost as master and addressed as slave by general call data a 178 8042a?avr?07/09 atmega16hvb/32hvb 27.7.4 slave transmitter mode in the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see figure 27-17 ). all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. figure 27-17. data transfer in slave transmitter mode to initiate the slave transmitter mode, twar and twcr must be in itialized as follows: the upper seven bits are the address to which t he two-wire serial interface will respond when addressed by a master. if the lsb is set, the twi will respond to the general call address (0x00), otherwise it will ignore the general call address. twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledgment of the device?s own slave add ress or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. if the direction bit is ?1? (read), the twi will operate in st mode, otherw ise sr mode is entered. after its own slave address and the write bit have been received, the twint flag is set and a valid status code can be read from twsr. the status c ode is used to determine the appropriate soft- ware action. the appropriate action to be taken for each status code is detailed in table 27-5 . the slave transmitter mode may also be entered if arbitration is lost while the twi is in the master mode (see state 0xb0). if the twea bit is written to zero during a transfer, the twi will transm it the last byte of the trans- fer. state 0xc0 or state 0xc8 will be entered, depending on whethe r the master receiver transmits a nack or ack after the final byte. the twi is switched to the not addressed slave mode, and will ignore the master if it continues the transfer . thus the master receiver receives all ?1? as serial data. state 0xc8 is entered if the master demands additional data bytes (by transmitting ack), even though the slave has transmitted the last byte (twea zero and expect- ing nack from the master). twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x device 3 device n sda scl ........ r1 r2 v bus device 2 master receiver device 1 slave transmitter 179 8042a?avr?07/09 atmega16hvb/32hvb while twea is zero, the twi does not respond to its own slave address. however, the two-wire serial bus is still monitored an d address recognition may resume at any time by setting twea. this implies that the twea bit may be used to temporarily isolate the twi from the two-wire serial bus. in all sleep modes other than idle mode, the clock system to the twi is turned off. if the twea bit is set, the interface can still acknowledge its own slave ad dress or the general call address by using the two-wire serial bus clock as a clock source. the part will then wake up from sleep and the twi will hold the scl clock will low during the wake up and until the twint flag is cleared (by writing it to one). further data tr ansmission will be carried out as normal, with the avr clocks running as normal. observe that if the avr is set up with a long start-up time, the scl line may be held low for a long ti me, blocking other data transmissions. note that the two-wire serial interface data register ? twdr ? does not reflect the last byte present on the bus when waking up from these sleep modes. table 27-5. status codes for slave transmitter mode status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0xa8 own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xb0 arbitration lost in sla+r/w as master; own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xb8 data byte in twdr has been transmitted; ack has been received load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xc0 data byte in twdr has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xc8 last data byte in twdr has been transmitted (twea = ?0?); ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 180 8042a?avr?07/09 atmega16hvb/32hvb figure 27-18. formats and states in the slave transmitter mode 27.7.5 miscellaneous states there are two status codes that do not correspond to a defined twi state, see table 27-6 . status 0xf8 indicates that no relevant information is available because the twint flag is not set. this occurs between other states, and when the twi is not involved in a serial transfer. status 0x00 indicates that a bus error has occurred during a two-wire serial bus transfer. a bus error occurs when a start or stop condition occurs at an illegal position in the format frame. examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. when a bus error occurs, twint is set. to recover from a bus error, the twsto flag must set and twint must be cleared by writing a logic one to it. this causes the twi to enter the not addressed slave mode and to clear the twsto flag (no other bits in twcr are affected). the sda and scl lines are released, and no stop condition is transmitted. s sla r a data a $a8 $b8 a $b0 reception of the own slave address and one or more data bytes last data byte transmitted. switched to not addressed slave (twea = '0') arbitration lost as master and addressed as slave n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the two-wire serial bus. the prescaler bits are zero or masked to zero p or s data $c0 data a a $c8 p or s all 1's a 181 8042a?avr?07/09 atmega16hvb/32hvb 27.7.6 combining several twi modes in some cases, several twi modes must be combined in order to complete the desired action. consider for example reading data from a serial eeprom. typically, such a transfer involves the following steps: 1. the transfer must be initiated. 2. the eeprom must be instructed what location should be read. 3. the reading must be performed. 4. the transfer must be finished. note that data is transmitted both from master to slave and vice versa. the master must instruct the slave what location it wants to read, requi ring the use of the mt mode. subsequently, data must be read from the slave, implying the use of the mr mode. thus, the transfer direction must be changed. the master must keep control of the bus during all these steps, and the steps should be carried out as an atomic operation. if this principle is violated in a multi-master sys- tem, another master can alter the data pointer in the eeprom between steps 2 and 3, and the master will read the wrong data lo cation. such a change in transfe r direction is accomplished by transmitting a repeated start between the trans mission of the address byte and reception of the data. after a repeated start, the master keeps ownership of the bus. the following figure shows the flow in this transfer. figure 27-19. combining several twi modes to access a serial eeprom 27.8 multi-master syst ems and arbitration if multiple masters are connected to the same bus, transmissions may be initiated simultane- ously by one or more of them. the twi standar d ensures that such situations are handled in such a way that one of the mast ers will be allowed to proceed wit h the transfer, and that no data will be lost in the process. an example of an ar bitration situation is depicted below, where two masters are trying to transmit data to a slave receiver. table 27-6. miscellaneous states status code (twsr) prescaler bits are 0 status of the two-wire serial bus and two-wire serial inter- face hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0xf8 no relevant state information available; twint = ?0? no twdr action no twcr action wait or proceed current transfer 0x00 bus error due to an illegal start or stop condition no twdr action 0 1 1 x only the internal hardware is affected, no stop condi- tion is sent on the bus. in all cases, the bus is released and twsto is cleared. master transmitter master receiver s = start rs = repeated start p = stop transmitted from master to slave transmitted from slave to master s sla+w a address a rs sla+r a data a p 182 8042a?avr?07/09 atmega16hvb/32hvb figure 27-20. an arbitration example several different scenarios may arise during arbitration, as described below: ? two or more masters are performing identical communication with the same slave. in this case, neither the slave nor any of the mast ers will know about the bus contention. ? two or more masters are accessing the same slave with different data or direction bit. in this case, arbitration will occur, either in the read/wri te bit or in the data bits. the masters trying to output a one on sda while an other master outputs a zero will lose the arbitration. losing masters will switch to not address ed slave mode or wait until the bus is free and transmit a new start condition, depending on application software action. ? two or more masters are access ing different slaves. in this ca se, arbitration will occur in the sla bits. masters trying to output a one on sd a while another master outputs a zero will lose the arbitration. masters losing ar bitration in sla will switch to slave mode to check if they are being addressed by the winning master. if addressed, they will switch to sr or st mode, depending on the value of the read/write bit. if they are not being addressed, they will switch to not addressed slave mode or wait until the bus is free and transmit a new start condition, depending on application software action. this is summarized in figure 27-21 . possible status values are given in circles. figure 27-21. possible status codes caused by arbitration device 1 master transmitter device 2 master transmitter device 3 slave receiver device n sda scl ........ r1 r2 v bus own address / general call received arbitration lost in sla twi bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free no arbitration lost in data direction ye s write data byte will be received and not ack will be returned data byte will be received and ack will be returned last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received read b0 68/78 38 sla start data stop 183 8042a?avr?07/09 atmega16hvb/32hvb 27.9 bus connect/disco nnect for two-wire serial interface the bus connect/disconnect module is an addition to the twi interface. based on a configura- tion bit, an interrupt can be generated either when the twi bus is connected or disconnected. figure 27-22 illustrates the bus connect/disconnect logic, where sda and scl are the twi data and clock lines, respectively. when the twi bus is connected, both the sd a and the scl lines will be come high simultane- ously. if the twbcip bi t is cleared, the interrupt will be executed if enabled. once the bus is connected, the twbcip bit should be set. this enables detection of when the bus is discon- nected, and prevents repetitive interrupts every time both the sda and scl lines are high (e.g. bus idle state). when the twi bus is disconne cted, both the sda and the sc l lines will become low simultane- ously. if the twbcip bit is set, the interrupt will be executed if enabled and if both lines remain low for a configurable time period. by adding this time constraint, unwanted interrupts caused by both lines going low during normal bus communication is prevented. figure 27-22. overview of bus connect/disconnect. delay element start output delay twbcsr sda scl set twbcif ir q twbdt twbcip 8-bit data bus 184 8042a?avr?07/09 atmega16hvb/32hvb 27.10 register description 27.10.1 twbr ? twi bit rate register ? bits 7:0 ? twi bit rate register twbr selects the division factor for the bit rate generator. the bit rate generator is a frequency divider which generates the scl clock frequency in the master modes. see ?bit rate generator unit? on page 163 for calculating bit rates. 27.10.2 twcr ? twi control register the twcr is used to control the operation of the twi. it is used to enable the twi, to initiate a master access by applying a start condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the twdr. it also indicates a write collision if data is attempted written to twdr while the regist er is inaccessible. ? bit 7 ? twint: twi interrupt flag this bit is set by hardware when the twi has finished its current job and expects application software response. if the i-bit in sreg and twie in twcr are set, the mcu will jump to the twi interrupt vector. while the twint flag is set, the scl low period is stretched. the twint flag must be cleared by software by writing a logic one to it. note that this flag is not automati- cally cleared by hardware when executing the interr upt routine. also note that clearing this flag starts the operation of the twi, so all accesses to the twi address register (twar), twi sta- tus register (twsr), and twi data register (twdr) must be complete before clearing this flag. ? bit 6 ? twea: twi enable acknowledge bit the twea bit controls the generation of the acknowledge pulse. if the twea bit is written to one, the ack pulse is generated on the twi bus if the following conditions are met: 1. the device?s own slave address has been received. 2. a general call has been received, while the twgce bit in the twar is set. 3. a data byte has been received in master receiver or slave receiver mode. by writing the twea bit to zero, the device can be virtually disconnected from the two-wire serial bus temporarily. address recognition can then be resumed by writing the twea bit to one again. ? bit 5 ? twsta: twi start condition bit the application writes the twsta bit to one when it desires to become a master on the two- wire serial bus. the twi hardware checks if the bus is available, and generates a start con- bit 76543210 (0xb8) twbr7 twbr6 twbr5 twbr4 twbr3 twbr2 twbr1 twbr0 twbr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 (0xbc) twint twea twsta twsto twwc twen ? twie twcr read/write r/w r/w r/w r/w r r/w r r/w initial value 0 0 0 0 0 0 0 0 185 8042a?avr?07/09 atmega16hvb/32hvb dition on the bus if it is free. however, if the bus is not free, t he twi waits until a stop condition is detected, and then generates a new start condition to claim the bus master status. twsta is cleared by the twi hardware when th e start condition has been transmitted. ? bit 4 ? twsto: twi stop condition bit writing the twsto bit to one in master mode will generate a stop condition on the two-wire serial bus. when the stop condition is exec uted on the bus, the twsto bit is cleared auto- matically. in slave mode, setting the twsto bit can be used to recover from an error condition. this will not generate a stop co ndition, but the twi returns to a well-defined unaddressed slave mode and releases the scl and sda lines to a high impedance state. ? bit 3 ? twwc: twi write collision flag the twwc bit is set when attempting to write to the twi data register ? twdr when twint is low. this flag is cleared by writing the twdr register when twint is high. ? bit 2 ? twen: twi enable bit the twen bit enables twi operation and activate s the twi interface. when twen is written to one, the twi takes control over the i/o pins connected to the scl and sda pins, enabling the slew-rate limiters and spike filters. if this bit is written to zero, the twi is switched off and all twi transmissions are terminated, regardless of any ongoing operation. ? bit 1 ? res: reserved bit this bit is a reserved bit an d will always read as zero. ? bit 0 ? twie: twi interrupt enable when this bit is written to one, and the i-bit in sreg is set, th e twi interrupt request will be acti- vated for as long as the twint flag is high. 27.10.3 twsr ? twi status register ? bits 7:3 ? tws: twi status these five bits reflect the status of the twi logic and the two-wire serial bus. the different sta- tus codes are described in table 27-2 on page 170 through table 27-5 on page 179 . note that the value read from twsr contains both the 5-bit status value and the 2-bit prescaler value. the application designer should mask the prescaler bi ts to zero when checking the status bits. this makes status checking independent of prescale r setting. this approach is used in this datasheet, unless otherwise noted. ? bit 2 ? res: reserved bit this bit is reserved and will always read as zero. ? bits 1:0 ? twps: twi prescaler bits these bits can be read and written, and control the bit rate prescaler. bit 76543210 (0xb9) tws7 tws6 tws5 tws4 tws3 ? twps1 twps0 twsr read/write rrrrrrr/wr/w initial value 1 1 1 1 1 0 0 0 186 8042a?avr?07/09 atmega16hvb/32hvb to calculate bit rates, see ?bit rate generator unit? on page 163 . the value of twps1:0 is used in the equation. 27.10.4 twdr ? twi data register in transmit mode, twdr contains the next byte to be transmitted. in receive mode, the twdr contains the last byte received. it is writable while the twi is not in the process of shifting a byte. this occurs when the twi interrupt flag (twint) is set by hardware. note that the data register cannot be initialized by the user before the first interrupt occurs. the data in twdr remains sta- ble as long as twint is set. while data is shifted out, data on the bus is simultaneously shifted in. twdr always contains the last byte present on the bus, except after a wake-up from a sleep mode by the twi interrupt. in this case, the conten ts of twdr is undefined. in the case of a lost bus arbitration, no data is lost in the transition from master to slave. handling of the ack bit is controlled automatically by the twi logic, the cpu cannot access the ack bit directly. ? bits 7:0 ? twd: twi data register these eight bits constitute the next data byte to be transmitted, or the latest data byte received on the two-wire serial bus. 27.10.5 twar ? twi (slave) address register the twar should be loaded with the 7-bit slave address (in the seven most significant bits of twar) to which the twi will respond when prog rammed as a slave transmitter or receiver, and not needed in the master modes. in multi-master systems, twar must be set in masters which can be addressed as slaves by other masters. the lsb of twar is used to enable recognition of the general call address (0x00). there is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. if a match is found, an interrupt request is generated. ? bits 7:1 ? twa: twi (slave) address register these seven bits constitute th e slave address of the twi unit. table 27-7. twi bit rate prescaler twps1 twps0 prescaler value 00 1 01 4 10 16 11 64 bit 76543210 (0xbb) twd7 twd6 twd5 twd4 twd3 twd2 twd1 twd0 twdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 bit 76543210 (0xba) twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce twar read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 0 187 8042a?avr?07/09 atmega16hvb/32hvb ? bit 0 ? twgce: twi general call recognition enable bit if set, this bit enables the recognition of a general call given over the two-wire serial bus. 27.10.6 twamr ? twi (slave) address mask register ? bits 7:1 ? twam: twi address mask the twamr can be loaded with a 7-bit slave addr ess mask. each of the bits in twamr can mask (disable) the corresponding address bits in the twi address register (twar). if the mask bit is set to one then the address match l ogic ignores the compare between the incoming address bit and the corresponding bit in twar. figure 27-23 shown the address match logic in detail. figure 27-23. twi address match logic, block diagram ? bit 0 ? res: reserved bit this bit is an unused bit in the atmega1 6hvb/32hvb, and will always read as zero. 27.10.7 twbcsr ? twi bus control and status register ? bit 7 - twbcif: twi bus connect/disconnect interrupt flag based on the twbcip bit, the twbcif bit is set when the twi bus is connected or discon- nected (1) . twbcif is cleared by hardware when exec uting the corresponding interrupt handling vector. alternatively, twbcif is cleared by writ ing a logic one to the flag. when the sreg i-bit, twbcie (twi bus connect/disconnect interrupt enable), and twbcif are set, the twi bus connect/disconnect interrupt is executed. if bo th sda and scl are high during reset, twbcif will be set after reset. otherwise twbcif will be cleared after reset. note: 1. the twen bit in the twcr register must be set for the bus connect/disconnect feature to be enabled. bit 76543210 (0xbd) twam[6:0] ?twamr read/write r/w r/w r/w r/w r/w r/w r/w r initial value 0 0 0 0 0 0 0 0 address match address bit comparator 0 address bit comparator 6..1 twar0 twamr0 address bit 0 bit 7 6 543 2 1 0 (0xbe) twbcif twbcie ? ? ? twbdt1 twbdt0 twbcip twbcsr read/write r/w r/w r r r r/w r/w r/w initial value x 0 000 0 0 0 188 8042a?avr?07/09 atmega16hvb/32hvb ? bit 6 - twbcie: twi bus connect/disconnect interrupt enable when the twbcie bit and the i-bit in the status register are set, the twi bus connect/discon- nect interrupt is enabled. the corresponding interrupt is executed if a twi bus connect/disconnect occurs, i.e., when the twbcie bit is set. ? bit 5:3 - res: reserved bits these bits are reserved bits in the atme ga16hvb/32hvb and will always read as zero. ? bit 2:1 - twbdt1, twbdt0: twi bus disconnect time-out period the twbdt bits decides how long both the tw i data (sda) and clock (scl) signals must be low before generating the twi bus disconnect interrupt. the different configuration values and their corresponding time-out periods are shown in table 27-8 . ? bit 0 - twbcip: twi bus connect/disconnect interrupt polarity the twbcip bit decide if the twi bus connec t/disconnect interrupt flag (twbcif) should be set on a bus connect or a bus disconnect. if twbcip is cleared, the twbcif flag is set on a bus connect. if twbcip is set, the twbcif flag is set on a bus disconnect. table 27-8. tw bus disconnect time-out period twbdt1 twbdt0 twi bus disconnect time-out period 0 0 250 ms 0 1 500 ms 1 0 1000 ms 1 1 2000 ms 189 8042a?avr?07/09 atmega16hvb/32hvb 28. debugwire on-chip debug system 28.1 features ? complete program flow control ? emulates all on-chip func tions, both digital and analog, except reset pin ? real-time operation ? symbolic debugging support (both at c and assembler source level, or for other hlls) ? unlimited number of prog ram break points (using software break points) ? non-intrusive operation ? electrical characteristics identical to real device ? automatic configuration system ? high-speed operation ? programming of non-volatile memories 28.2 overview the debugwire on-chip debug system uses a one-wire, bi-directional interface to control the program flow, execute avr instructions in the cpu and to program the different non-volatile memories. 28.3 physical interface when the debugwire enable (dwen) fuse is programmed and lock bits are unprogrammed, the debugwire system within the target device is activated. the reset port pin is configured as a wire-and (open-drain) bi-directional i/o pin with pull-up enabled and becomes the commu- nication gateway between target and emulator. figure 28-1. the debugwire setup figure 28-1 shows the schematic of a target mcu, with debugwire enabled, and the emulator connector. the system clock is not affected by debugwire and will always be the clock source selected by the oscsel fuses. dw gnd dw(reset) vcc 1.8 - 5.5v dw gnd dw(reset) vcc 3.0 - 5.5v 190 8042a?avr?07/09 atmega16hvb/32hvb when designing a system where debugwire will be used, the following observations must be made for correct operation: ? pull-up resistors on the dw/(reset) line must not be smaller than 10k . the pull-up resistor is not required for debugwire functionality. ? connecting the reset pin directly to v cc will not work. ? capacitors connected to th e reset pin must be disconne cted when using debugwire. ? all external reset sources must be disconnected. 28.4 software break points debugwire supports program memory break points by the avr break instruction. setting a break point in avr studio ? will insert a break instruction in the program memo ry. the instruc- tion replaced by the break instru ction will be stored. when program execution is continued, the stored instruction will be execut ed before continuing from the program memory. a break can be inserted manually by putting the break instruction in the program. the flash must be re-programmed each time a break point is changed. this is automatically handled by avr studio th rough the debugwire inte rface. the use of brea k points will therefore reduce the flash data retention. devices used for debugging purposes should not be shipped to end customers. 28.5 limitations of debugwire the debugwire communication pin (dw) is physica lly located on the same pin as external reset (reset). an external reset source is therefore not supported when the debugwire is enabled. a programmed dwen fuse enable s some parts of the clock system to be running in all sleep modes. this will increase the power consumption while in sleep. thus, the dwen fuse should be disabled when debugwire is not used. when using debugwire to access the flash (reading/writing), one must make sure the spmcsr register is not locked from before. if spmcsr is locked the result of the operation may not be as expected. 28.6 register description the following section describes the registers used with the debugwire. 28.6.1 dwdr ? debugwire data register the dwdr register provides a communication channel from the running program in the mcu to the debugger. this register is only accessible by the debugwire and can therefore not be used as a general purpose register in the normal operations. bit 76543210 0x31 (0x51) dwdr[7:0] dwdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 191 8042a?avr?07/09 atmega16hvb/32hvb 29. boot loader support ? read -while-write self-programming 29.1 features ? read-while-write self-programming ? flexible boot memory size ? high security (separate boot lock bits for a flexible protection) ? separate fuse to select reset vector ? optimized page (1) size ? code efficient algorithm ? efficient read-modify-write support note: 1. a page is a section in the flash consisting of several bytes (see ?page size? on page 211 ) used during programming. the page organiz ation does not affect normal operation. 29.2 overview the boot loader support provides a real read- while-write self-programming mechanism for downloading and uploading program code by the m cu itself. this feature a llows flexible applica- tion software updates controlled by the mcu using a flash-resident boot loader program. the boot loader program can use any available data interface and associated protocol to read code and write (program) that code into the flash memory, or read the code from the program mem- ory. the program code within the boot loader section has the capability to write into the entire flash, including the boot loader memory. the b oot loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. the size of the boot loader memory is configurable with fuses and t he boot loader has two separate sets of boot lock bits which can be set indepen dently. this gives the user a uniq ue flexibility to select differ- ent levels of protection. 29.3 application and boot loader flash sections the flash memory is organized in two main sections, the application section and the boot loader section. the size of the different sections is configured by the bootsz fuses as shown in table 29-5 on page 204 and figure 29-2 . these two sections can have different level of pro- tection since they have different sets of lock bits. 29.3.1 application section the application section is the section of the flash that is used for storing the application code. the protection level for the application section can be selected by the application boot lock bits (boot lock bits 0), see table 30-2 on page 208 . the application section can never store any boot loader code since the spm instruction is disabled when executed from the application section. 29.3.2 bls ? boot loader section while the application section is used for storing the application code, the the boot loader soft- ware must be located in the bls since the spm instruction can initiate a programming when executing from the bls only. the spm instruct ion can access the entire flash, including the bls itself. the protection level for the boot loader section can be selected by the boot loader lock bits (boot lock bits 1), see table 30-2 on page 208 . 192 8042a?avr?07/09 atmega16hvb/32hvb 29.4 read-while-write and no r ead-while-write flash sections whether the cpu supports read-while-write or if the cpu is halted during a boot loader soft- ware update is dependent on which address that is being programmed. in addition to the two sections that are configurable by the bootsz fuses as described above, the flash is also divided into two fixed sections, the read-whi le-write (rww) section and the no read-while- write (nrww) section. the limit between the rww- and nrww sections is given in table 29- 6 on page 204 and figure 29-2 on page 194 . the main difference between the two sections is: ? when erasing or writing a page located inside the rww section, the nrww section can be read during the operation. ? when erasing or writing a page located inside the nrww section, the cpu is halted during the entire operation. note that the user software can never read any code that is located inside the rww section dur- ing a boot loader software operation. the syntax ?read-while-write section? refers to which section that is being programmed (erased or written), not which section that actually is being read during a boot loader software update. 29.4.1 rww ? read-while-write section if a boot loader software update is programming a page inside the rww section, it is possible to read code from the flash, but only code that is located in the nrww section. during an on- going programming, the software must ensure that the rww section never is being read. if the user software is trying to read code that is located inside the rww section (i.e., by a call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown state. to avoid this, the interrupts should either be disabled or moved to the boot loader sec- tion. the boot loader section is always located in the nrww section. the rww section busy bit (rwwsb) in the store program memory cont rol and status register (spmcsr) will be read as logical one as long as the rww section is blocked for reading. after a programming is com- pleted, the rwwsb must be cleared by software before reading code located in the rww section. see ?spmcsr ? store program memory control and status register? on page 206 for details on how to clear rwwsb. 29.4.2 nrww ? no read-while-write section the code located in the nrww section can be read when the boot loader software is updating a page in the rww section. when the boot loader code updates the nrww section, the cpu is halted during the entire page erase or page write operation. table 29-1. read-while-write features which section does the z-pointer address during the programming? which section can be read during programming? cpu halted? read-while-write supported? rww section nrww section no yes nrww section none yes no 193 8042a?avr?07/09 atmega16hvb/32hvb figure 29-1. read-while-write vs. no read-while-write read-while-write (rww) section no read-while-write (nrww) section z-pointer addresses rww section z-pointer addresses nrww section cpu is halted during the operation code located in nrww section can be read during the operation 194 8042a?avr?07/09 atmega16hvb/32hvb figure 29-2. memory sections note: 1. the parameters in the figure above are given in table 29-5 on page 204 . 29.5 boot loader lock bits if no boot loader capability is n eeded, the entire flash is available for application code. the boot loader has two separate sets of boot lock bits which can be set independently. this gives the user a unique flexibility to sele ct different levels of protection. the user can select: ? to protect the entire flash from a software update by the mcu. ? to protect only the boot loader flash section from a software update by the mcu. ? to protect only the application flash section from a software update by the mcu. ? allow software update in the entire flash. see table 30-2 on page 208 for further details. the boot lock bits can be set in software and in serial or parallel programming mode, but they can be cleared by a chip erase command only. the general write lock (lock bit mode 2) does not control the programming of the flash mem- ory by spm instruction. similarly, the general read/write lock (lock bit mode 1) does not control reading nor writing by lpm/spm, if it is attempted. 0x0000 flashend program memory bootsz = '11' application flash section boot loader flash section flashend program memory bootsz = '10' 0x0000 program memory bootsz = '01' program memory bootsz = '00' application flash section boot loader flash section 0x0000 flashend application flash section flashend end rww start nrww application flash section boot loader flash section boot loader flash section end rww start nrww end rww start nrww 0x0000 end rww, end application start nrww, start boot loader application flash section application flash section application flash section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section end application start boot loader end application start boot loader end application start boot loader 195 8042a?avr?07/09 atmega16hvb/32hvb 29.6 entering the b oot loader program entering the boot loader takes place by a jump or call from the application program. this may be initiated by a trigger such as a command received via the twi interface. alternatively, the boot reset fuse can be programmed so that the reset vector is pointing to the boot flash start address after a reset. in this case, the boot loader is started after a reset. after the application code is loaded, the program can start executing the application code. note that the fuses cannot be changed by the mcu itself. this means that once the boot reset fuse is programmed, the reset vector will always point to the boot loader reset and th e fuse can only be changed through the serial or parallel programming interface. note: 1. ?1? means unprogrammed, ?0? means programmed table 29-2. boot reset fuse (1) bootrst reset address 1 reset vector = application reset (address 0x0000) 0 reset vector = boot loader reset (see table 29-5 on page 204 ) 196 8042a?avr?07/09 atmega16hvb/32hvb 29.7 addressing the flash during self-programming the z-pointer is used to address the spm commands. since the flash is organized in pages (see ?fuse bits? on page 209 ), the program counter can be treated as having two different sections. one sect ion, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. this is shown in figure 29-3 . note that the page erase and page write operations are addressed independently. therefore it is of major importance that the boot loader software addresses the same page in both the page erase and page write operation. once a program- ming operation is initiated, the address is latched and the z-pointer can be used for other operations. the only spm operation that does not use the z-pointer is setting the boot loader lock bits. the content of the z-pointer is ignored and will have no effect on the operation. the lpm instruction does also use the z-pointer to store the address. since this instruction addresses the flash byte-by-byte, also the lsb (bit z0) of the z-pointer is used. figure 29-3. addressing the flash during spm (1) note: 1. the different variables used in figure 29-3 are listed in table 29-7 on page 204 and table 29- 10 on page 205 . bit 151413121110 9 8 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30) z7z6z5z4z3z2z1z0 76543210 program memory 0 1 15 z - register bit 0 zpagemsb word address within a page page address within the flash zpcmsb instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter 197 8042a?avr?07/09 atmega16hvb/32hvb 29.8 self-programming the flash the program memory is updated in a page by page fashion. before programming a page with the data stored in the temporary page buffer, the page must be erased. the temporary page buf- fer is filled one word at a time using spm and the buffer can be filled either before the page erase command or between a page erase and a page write operation: alternative 1, fill the bu ffer before a page erase ? fill temporary page buffer ? perform a page erase ? perform a page write alternative 2, fill the bu ffer after page erase ? perform a page erase ? fill temporary page buffer ? perform a page write if only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. when using alternative 1, the boot loader provides an effective read-modify-write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. if alter- native 2 is used, it is not possible to read the old data while loading since the page is already erased. the temporary page buffer can be accessed in a random sequence. it is essential that the page address used in both the page erase and page write operation is addressing the same page. see ?simple assembly code example for a boot loader? on page 202 for an assembly code example. 29.8.1 performing page erase by spm to execute page erase, set up the address in the z-pointer, write ?x0000011? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage in the z-register. other bits in the z-pointer will be ignored during this operation. ? page erase to the rww section: the nrww section can be read during the page erase. ? page erase to the nrww section: the cpu is halted during the operation. 29.8.2 filling the temporary buffer (page loading) to write an instruction word, set up the address in the z-pointer and data in r1:r0, write ?x0000001? to spmcsr and execute spm within four clock cycles after writing spmcsr. the content of pcword in the z-register is used to address the data in the temporary buffer. the temporary buffer will auto-erase after a page write operation or by writing the rwwsre bit in spmcsr. it is also erased after a system reset. note that it is not possible to write more than one time to each address without erasing the temporary buffer. 198 8042a?avr?07/09 atmega16hvb/32hvb 29.8.3 performing a page write to execute page write, set up the address in the z-pointer, write ?x0000101? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be writte n to pcpage. other bits in th e z-pointer will be ignored during this operation. ? page write to the rww section: the nrww section can be read during the page write. ? page write to the nrww section: the cpu is halted during the operation. 29.8.4 using the spm interrupt if the spm interrupt is en abled, the spm interrupt will genera te a constant in terrupt when the spmen bit in spmcsr is cleared. this means th at the interrupt can be used instead of polling the spmcsr register in software. when using the spm interrupt, the interrupt vectors should be moved to the bls section to avoid that an interrupt is accessing the rww section when it is blocked for reading. how to move the interrupts is described in ?interrupts? on page 52 . 29.8.5 consideration while updating bls special care must be taken if the user allows the boot loader section to be updated by leaving boot lock bit11 unprogrammed. an accidental write to the boot loader itself can corrupt the entire boot loader, and further software updates might be impossible. if it is not necessary to change the boot loader software itself, it is recommended to program the boot lock bit11 to protect the boot loader software from any internal software changes. 29.8.6 prevent reading the rww section during self-programming during self-programming (either page erase or page write), the rww section is always blocked for reading. the user software itself must prevent that this section is addressed during the self programming operation. the rwwsb in the spmcsr will be set as long as the rww section is busy. during self-programming the interrupt vector table should be moved to the bls as described in ?interrupts? on page 52 , or the interrupts must be disabled. before addressing the rww section after the programming is completed, the user software must clear the rwwsb by writing the rwwsre. see ?simple assembly code example for a boot loader? on page 202 for an example. 29.8.7 setting the lock bits by spm to set the lock bits, write the desired data to r0, write ?x0001001? to spmcsr and execute spm within four clock cycles after writing spmcsr. see table 30-2 on page 208 for how the different settings of the lock bits affect the flash access. if bits 5:0 in r0 are cleare d (zero), the corresponding loc k bit will be programmed if an spm instruction is executed within four cycles after lbset and spmen are set in spmcsr. the z- pointer is don?t care during this operation, but fo r future compatibility it is recommended to load the z-pointer with 0x0001 (same as used for reading the lo ck bits). for future compatibility it is also recommended to set bits 7 and 6 in r0 to ?1? when writing the lock bits. when program- ming the lock bits the entire flas h can be read during the operation. bit 76543210 r0 1 1 blb12 blb11 blb02 blb01 lb2 lb1 199 8042a?avr?07/09 atmega16hvb/32hvb 29.8.8 reading the fuse and lock bits from software it is possible to read both the fuse and lock bits from software. to read the lock bits, load the z-pointer with 0x0001 and set the lbset and spmen bits in spmcsr. when an lpm instruc- tion is executed within three cpu cycles after the lbset and spmen bits are set in spmcsr, the value of the lock bits will be loaded in the dest ination register. the lbset and spmen bits will auto-clear upon completion of reading the lock bits. when lbset and spme n are cleared, lpm will work as described in the ? avr instruction se t? description. the algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. to read the fuse low byte, load the z-pointer with 0x0000 and set the lbset and spmen bits in spmcsr. when an lpm instruction is executed within three cycles after the lbset and spmen bits are set in the spmcsr, the value of t he fuse low byte (flb) will be loaded in the destination register as shown below. refer to table 30-4 on page 210 for a detailed description and mapping of the fuse low byte. similarly, when reading the fuse high byte, load 0x0003 in the z-pointer. when an lpm instruc- tion is executed within three cycles after the lbset and spmen bits are set in the spmcsr, the value of the fuse high byte (fhb) will be load ed in the destination re gister as shown below. refer to table 30-3 on page 209 for detailed description and mapping of the fuse high byte. fuse and lock bits that are programmed, will be read as zero. fuse and lock bits that are unprogrammed, will be read as one. 29.8.9 reading the signature row from software to read the signature row from software, load the z-pointer with the signature byte address given in table 29-3 and set the sigrd and spmen bits in spmcsr. when an lpm instruction is executed within three cpu cycles after t he sigrd and spmen bits are set in spmcsr, the signature byte value will be loaded in the desti nation register. the sigrd and spmen bits will auto-clear 6 cycles after writing to spmcsr, which is locked fo r further writing during these cycles. when sigrd and spmen are cleared, lpm will work as described in the instruction set manual bit 76543210 rd ? ? blb12 blb11 blb02 blb01 lb2 lb1 bit 76543210 rd flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 bit 76543210 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 table 29-3. signature row addressing. signature byte description z-pointer address device id 0, manufacture id 00h device id 1, flash size 02h device id 2, device 04h fosccal (1) 01h fosc segment (2) 03h reserved 05h 200 8042a?avr?07/09 atmega16hvb/32hvb notes: 1. default fosccal value after reset. slow rc period l 06h slow rc period h (3) 07h slow rc temp prediction l 08h slow rc temp prediction h (4) 09h ulp rc frq (5) 0ah slow rc frq (6) 0bh ulp rc temp prediction coefficient l och ulp rc temp prediction coefficient h (7) odh ulp rc period l oeh ulp rc period h (8) ofh bgcrr calibration byte 10h bgccr calibration byte 11h reserved 12h:17h vptat cal l 18h vptat cal h (9) 19h v-adc cell1 gain calibration word l 1ah v-adc cell1 gain calibration word h (10) 1bh v-adc cell2 gain calibration word l 1ch v-adc cell2 gain calibration word h (10) 1dh v-adc cell3 gain calibration word l 1eh v-adc cell3 gain calibration word h (10) 1fh v-adc cell4 gain calibration word l 20h v-adc cell4 gain calibration word h (10) 21h v-adc cell1 offset (11) 22h v-adc cell2 offset (11) 23h v-adc cell3 offset (11) 24h v-adc cell4 offset (11) 25h v-adc0 gain calibration word l 26h v-adc0 gain calibration word h (12) 27h v-adc1 gain calibration word l 28h v-adc1 gain calibration word h (13) 29h v-adc adc0 offset (14) 2ah v-adc adc1 offset (14) 2bh reserved 2ch:2fh t hot (15) 30h table 29-3. signature row addressing. (continued) signature byte description z-pointer address 201 8042a?avr?07/09 atmega16hvb/32hvb 2. fosccal setting used to smooth the transition from one segment to the next when calibrating the fast rc oscillator. 3. 8 prescaled slow rc periods in s using the oscillator sampling interface (@t hot c). 4. slow rc oscillator frequency temperature drift prediction value. 5. ulp rc oscillator frequency in khz (@ t hot c). 6. slow rc oscillator frequency in khz (@t hot c). 7. ulp rc oscillator frequency temperature drift prediction value. 8. 8 prescaled ulp rc periods in s using the oscillator sampling interface (@t hot c). 9. calibration word used to calculate the abs olute temperature in kelvin from a vtemp conversion. 10. calibration word used to compensate for gain error in v-adc cells. 11. calibration byte used to compensate for offset in v-adc cells. 12. calibration word used to compensate for gain error in adc0. 13. calibration word used to compensate for gain error in adc1. 14. calibration byte used to compensate for offset in adc0 and adc1. 15. hot temperature used for factory calibration in c. all other addresses are reserved for future use. 29.8.10 spmcsr writing restrictions writing any other combination than ?100001?, ?010001?, ?001001?, ?000101?, ?000011? or ?000001? in the lower six bits will have no effect. spmcsr is locked for writing under the following conditions: ? one or more of the bits 5:0 in spmcsr is set to 1 ? during eeprom write (status bit eewe in eecr is set) spmcsr will be cleared at the following events: ? on completion of successful exec ution the following instructions: ? lpm with lbset and spmen set ? spm with lbset and spmen set ? spm with pgers and spmen set ? spm with pgwrt and spmen set ? spm with spmen set ? six cycles after writing spmcsr if an y other or no lpm/spm is executed 29.8.11 programming time for flash when using spm the fast rc oscillator is used to time flash accesses. table 29-4 shows the typical program- ming time for flash accesses from the cpu. note: 1. minimum and maximum programming time is per individual operation. table 29-4. spm programming time (1) symbol min programming ti me max programming time flash write (page erase, page write, and write lock bits by spm) 3.7 ms 4.5 ms 202 8042a?avr?07/09 atmega16hvb/32hvb 29.8.12 simple assembly code example for a boot loader ;-the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by the y pointer ; the first data location in flash is pointed to by the z-pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the do_spm sub routine). only code inside nrww section ; can be read during self-programming (page erase and page write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-it is assumed that either the interrupt table is moved to the ; boot loader section or that the interrupts are disabled. .equ pagesizeb = pagesize*2 ;pagesizeb is page size in bytes, not words .org smallbootstart write_page: ; page erase ldi spmcrval, (1< 205 8042a?avr?07/09 atmega16hvb/32hvb note: 1. z0: should be zero for all spm commands, byte select for the lpm instruction. see ?addressing the flash during self-programming? on page 196 for details about the use of z-pointer during self-programming. 29.8.14 atmega32hvb boot loader parameters in table 29-8 through table 29-10 , the parameters used in the description of the self-program- ming are given note: 1. the different bootsz fuse configurations are shown in figure 29-2 for details about these two section, see ?nrww ? no read-while-write section? on page 192 and ?rww ? read-while-write section? on page 192 . table 29-8. boot size configuration (1) bootsz1 bootsz0 boot size pages application flash section boot loader flash section end application section boot reset address (start boot loader section) 1 1 256 words 4 0x0000 - 0x3eff 0x3f00 - 0x3fff 0x3eff 0x3f00 1 0 512 words 8 0x0000 - 0x3dff 0x3e00 - 0x3fff 0x3dff 0x3e00 0 1 1024 words 16 0x0000 - 0x3bff 0x3c00 - 0x3fff 0x3bff 0x3c00 0 0 2048 words 32 0x0000 - 0x37ff 0x3800 - 0x3fff 0x37ff 0x3800 table 29-9. read-while-write limit (1) section pages address read-while-write section (rww) 224 0x0000 - 0x37ff no read-while-write section (nrww) 32 0x3800 - 0x3fff table 29-10. explanation of different variables used in figure 29-3 on page 196 and the map- ping to the z-pointer (1) variable corresponding z-value description pcmsb 13 most significant bit in the program counter. (the program counter is 14 bits pc[13:0]) pag e m s b 5 most significant bit which is used to address the words within one page (64 words in a page requires six bits pc [5:0]). zpcmsb z14 bit in z-register that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z6 bit in z-register that is mapped to pcmsb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[13:6] z13:z7 program counter page address: page select, for page erase and page write pcword pc[5:0] z6:z1 program counter word address: word select, for filling temporary buffer (must be zero during page write operation) 206 8042a?avr?07/09 atmega16hvb/32hvb note: 1. z0: should be zero for all spm commands, byte select for the lpm instruction. see ?addressing the flash during self-programming? on page 196 for details about the use of z-pointer during self-programming. 29.9 register description 29.9.1 spmcsr ? store program memory control and status register the store program memory control and status register contains the control bits needed to con- trol the boot loader operations. ? bit 7 ? spmie: spm interrupt enable when the spmie bit is written to one, and the i-bit in the status register is set (one), the spm ready interrupt will be enabled. the spm ready in terrupt will be ex ecuted as long as the spmen bit in the spmcsr register is cleared. ? bit 6 ? rwwsb: read-while-write section busy when a self-programming (page erase or page write) operation to the rww section is initi- ated, the rwwsb will be set (one ) by hardware. when the rwws b bit is set, the rww section cannot be accessed. the rwwsb bit will be cleared if the rwwsre bit is written to one after a self-programming operation is completed. alter natively the rwwsb bit will automatically be cleared if a page load operation is initiated. ? bit 5 - sigrd: signature row read if this bit is written to one at the same time as spmen, the next lpm instruction within three clock cycles will read a byte from the signature row into the destination register. see ?reading the signature row from software? on page 199 for details. an spm instruction within four cycles after sigrd and spmen are set will have no effect. this operation is reserved for future use and should not be used. ? bit 4 ? rwwsre: read-while-write section read enable when programming (page erase or page write) to the rww section, the rww section is blocked for reading (the rwwsb will be set by hardware). to re-enable the rww section, the user software must wait unt il the programming is complet ed (spmen will be cl eared). then, if the rwwsre bit is written to one at the same time as spmen, the next spm instruction within four clock cycles re-enables the rww secti on. the rww section cannot be re-enabled while the flash is busy with a page erase or a page wr ite (spmen is set). if the rwwsre bit is writ- ten while the flash is being loaded, the flas h load operation will abort and the data loaded will be lost. ? bit 3 ? lbset: lock bit set if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles sets lock bits, according to the data in r0. the data in r1 and the address in the z- pointer are ignored. the lbset bit will automatically be cleared up on completion of the lock bit set, or after six cycles if no spm instruction is executed within four clock cycles. bit 7 6 5 4 3 2 1 0 0x37 (0x57) spmie rwwsb sigrd rwwsre lbset pgwrt pgers spmen spmcsr read/write r/w r r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 207 8042a?avr?07/09 atmega16hvb/32hvb an lpm instruction within thre e cycles after lbset and spmen are set in the spmcsr regis- ter, will read either the lock bits or the fuse bits (depending on z0 in the z-pointer) into the destination register. see ?reading the fuse and lock bits? on page 224 for details. ? bit 2 ? pgwrt: page write if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page write, with the data stored in the temporary buffer. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgwrt bit will auto-clear upon completion of a page write, or after six cycle s if no spm instruction is exe- cuted within four clock cycles. the cpu is halted during the entire page write operation if the nrww section is addressed. ? bit 1 ? pgers: page erase if this bit is written to one at the same time as spmen, the next spm instruction within four clock cycles executes page erase. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgers bi t will auto-clear upon comp letion of a page erase, or after six cycles if no spm in struction is executed within four clock cycles. the cpu is halted during the entire page write operation if the nrww section is addressed. ? bit 0 ? spmen: store program memory enable this bit enables the spm instruction for the next four clock cycles. if written to one together with either rwwsre, lbset, pgwrt? or pgers, the following spm instruct ion will have a special meaning, see description above. if only spmen is written, the following spm instruction will store the value in r1:r0 in the temporary page buffer addressed by the z-pointer. the lsb of the z-pointer is ignored. the spmen bit will aut o-clear upon completion of an spm instruction, or after six cycles if no spm instruction is executed within four clock cycles. during page erase and page write, the spmen bit remains high until the operation is completed. 208 8042a?avr?07/09 atmega16hvb/32hvb 30. memory programming 30.1 program and data memory lock bits the atmega16hvb/32hvb provides six lock bits which can be left unprogrammed (?1?) or can be programmed (?0?) to obtain the additional features listed in table 30-2 . the lock bits can only be erased to ?1? with the chip erase command. note: 1. ?1? means unprogrammed, ?0? means programmed table 30-1. lock bit byte (1) lock bit byte bit no description default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) blb12 5 boot lock bit 1 (unprogrammed) blb11 4 boot lock bit 1 (unprogrammed) blb02 3 boot lock bit 1 (unprogrammed) blb01 2 boot lock bit 1 (unprogrammed) lb2 1 lock bit 1 (unprogrammed) lb1 0 lock bit 1 (unprogrammed) table 30-2. lock bit protection modes (1)(2) memory lock bits protection type lb mode lb2 lb1 1 1 1 no memory lock features enabled. 210 further programming of the flash and eeprom is disabled in parallel and serial programming mode. the fuse bits are locked in both serial and parallel programming mode. (1) 300 further programming and verification of the flash and eeprom is disabled in parallel and serial programming mode. the boot lock bits and fuse bits are locked in both serial and parallel programming mode. (1) blb0 mode blb02 blb01 1 1 1 no restrictions for spm or lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 300 spm is not allowed to write to the application section, and lpm executing from the boot loader sect ion is not allowed to read from the application section. if interr upt vectors are placed in the boot loader section, interrupts are di sabled while executing from the application section. 401 lpm executing from the boot loader section is not allowed to read from the application section. if in terrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 209 8042a?avr?07/09 atmega16hvb/32hvb notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed 30.2 fuse bits the atmega16hvb/32hvb has two fuse bytes. table 30-4 and table 30-3 describe briefly the functionality of all the fuses and how they are mapped into the fuse byte. note that the fuses are read as logical zero, ?0?, if they are programmed. 30.2.1 high byte notes: 1. the default duvrdinit should not be changed. duvrdinit= ?1? is reserved for future use. 2. the default value of bootsz1:0 results in maximum boot size. blb1 mode blb12 blb11 1 1 1 no restrictions for spm or lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to the boot loader section, and lpm executing from the application sect ion is not allowed to read from the boot loader section. if inte rrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. 401 lpm executing from the application section is not allowed to read from the boot loader section. if in terrupt vectors are placed in the application section, interrupts are disabled while executing from the boot loader section. table 30-2. lock bit protection modes (1)(2) (continued) memory lock bits protection type table 30-3. fuse high byte bit no fuse high byte description default value 7:5 ? 4 duvrdinit (1) reset value of duvrdregister 0 (programmed) 3 dwen enable debugwire 1 (unprogrammed) 2 bootsz1 select boot size 0 (programmed) (2) 1 bootsz0 select boot size 0 (programmed) (2) 0 bootrst select reset vector 1 (unprogrammed) 210 8042a?avr?07/09 atmega16hvb/32hvb 30.2.2 low byte notes: 1. the watchdog is enabled/disabling by writi ng to the watchdog timer control and status reg- ister (wdtcsr). but as a fail-safe, the wdton fuse can be used to force the watchdog to run in system reset mode. 2. the sutx fuse bits are used to configure the st artup time from sleep or reset. by default the longest startup time is selected. 3. the default oscsel1:0 setting should not be ch anged. oscsel1:0="00" is reserved for test purpose. other values are reserved for future use. the status of the fuse bits is not affected by chip erase. note that the fuse bits are locked if lock bit1 (lb1) is programmed. program the fuse bits before programming the lock bits. 30.2.3 latching of fuses the fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves programming mode. this does not apply to the eesave fuse which will take effect once it is programmed. the fuse s are also latched on power-up in normal mode. 30.3 signature bytes all atmel microcontrollers have a three-byte signature code which identifies the device. this code can be read in both programming mode, also when the device is locked. the three bytes reside in a separate address space. the sig nature bytes of atmega16hvb/32hvb is given in table 30-5 . table 30-4. fuse low byte bit no fuse low byte description default value 7 wdton watchdog timer always on 1 (unprogrammed) (1) 6 eesave eeprom memory is preserved through the chip erase 1 (unprogrammed, eeprom not preserved) 5 spien enable serial programmable data downloading 0 (programmed, spi programming enabled) 4 sut2 select start-up time 1 (unprogrammed) (2) 3 sut1 select start-up time 1 (unprogrammed) (2) 2 sut0 select start-up time 1 (unprogrammed) (2) 1 oscsel1 oscillator select 1(unprogrammed) (3) 0 oscsel0 oscillator select 0(programmed) (3) table 30-5. device id part signature bytes address 0x000 0x001 0x002 atmega16hvb 0x1e 0x94 0x0d atmega32hvb 0x1e 0x95 0x10 211 8042a?avr?07/09 atmega16hvb/32hvb 30.4 calibration bytes the atmega16hvb/32hvb has calibration bytes for the rc oscillators, internal voltage refer- ence, internal temperature reference and each differential cell voltage input. these bytes reside in the signature address space. see ?reading the signature row from software? on page 199 for details. 30.5 page size 30.6 serial programming both the flash and eeprom memo ry arrays can be programmed using the serial spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and miso (out- put). after reset is set low, the programming enable instruction needs to be executed first before program/erase operations can be executed. note, in table 30-10 on page 212 , the pin mapping for spi programming is listed. not all pa rts use the spi pins dedicated for the internal spi interface. table 30-6. no. of words in a page and no. of pages in the flash, atmega16hvb flash size page size pcword no. of pages pcpage pcmsb 8k words (16k bytes) 64 words pc[5:0] 128 pc[12:6] 12 table 30-7. no. of words in a page and no. of pages in the flash, atmega32hvb flash size page size pcword no. of pages pcpage pcmsb 16k words (32k bytes) 64 words pc[5:0] 256 pc[13:6] 13 table 30-8. no. of words in a page and no. of pages in the eeprom, atmega16hvb eeprom size page size pcword no. of pages pcpage eeamsb 512 bytes 4 bytes eea[1:0] 128 eea[8:2] 8 table 30-9. no. of words in a page and no. of pages in the eeprom, atmega32hvb eeprom size page size pcword no. of pages pcpage eeamsb 1k bytes 4 bytes eea[1:0] 256 eea[9:2] 9 212 8042a?avr?07/09 atmega16hvb/32hvb figure 30-1. serial programming and verify. when programming the eeprom, an auto-erase cycle is built into the self-timed programming operation (in the serial mode only) and there is no need to first execute the chip erase instruction. the chip erase operation turns the content of every memory location in both the program and eeprom arrays into 0xff. depending on oscsel fuses, a valid clock must be present. the minimum low and high peri- ods for the serial clock (sck) input are defined as follows: low: > 2.2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz high: > 2.2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz 30.6.1 serial programming algorithm when writing serial data to the atmega16hvb/ 32hvb, data is clocked on the rising edge of sck. when reading data from the at mega16hvb/32hvb, data is clocke d on the falling edge of sck. see ?serial programming characteristics? on page 237 for timing details. to program and verify the atmega16hvb/32hvb in the serial programming mode, the follow- ing sequence is recommended (see four byte instruction formats in table 30-12 on page 214 ): 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. in some sys- tems, the programmer can not guarantee that sck is held low during power-up. in this table 30-10. pin mapping serial programming symbol pins i/o description sck pb5 i serial clock mosi pb6 i serial data in miso pb7 o serial data out v cc g n d sck miso mosi reset +3.3 - 4.5 v v cc g n d sck miso mosi reset +3.3 - 4.5 v 213 8042a?avr?07/09 atmega16hvb/32hvb case, reset must be given a positive pulse of at least two cpu clock cycles duration after sck has been set to ?0?. 2. wait for at least 20 ms and enable serial programming by sending the programming enable serial instruction to pin mosi. 3. the serial programming instructions will not wo rk if the communication is out of synchro- nization. when in sync. the second byte (0x53), will echo back wh en issuing the third byte of the programming enable instruction. whether the echo is correct or not, all four bytes of the instruction must be transmitted. if the 0x53 did not echo back, give reset a positive pulse and issue a new programming enable command. 4. the flash is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 5 lsb of the address and data together with the load program memory page instruction. to ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. the program memory page is stored by loading the write program memory page instruction with the 6 msb of the address. if polling (rdy/bsy) is not used, the user must wait at least t wd_flash before issuing the next page. (see table 30-11 .) accessing the serial programming interface before the flash write operation completes can result in incorrect programming. 5. a: the eeprom array is programmed one byte at a time by supplying the address and data together with the appropria te write instruction. an eeprom memory location is first automatically erased before new data is written. if polling (rdy/bsy) is not used, the user must wait at least t wd_eeprom before issuing the next byte. (see table 30-11 .) in a chip erased device, no 0xffs in the data file(s) need to be programmed. b: the eeprom array is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 2 lsb of the address and data together with the load eeprom memory page instruction. the eeprom memory page is stored by loading the write eeprom memory page instruction with the 6 msb of the address. when using eeprom page access only byte locations loaded with the load eeprom memory page instruction is altered. th e remaining locations remain unchanged. if polling (rdy/bsy) is not used, the used must wait at least t wd_eeprom before issuing the next page (see table 30-8 on page 211 ). in a chip erased device, no 0xff in the data file(s) need to be programmed. 6. any memory location can be verified by using the read instruction which returns the con- tent at the selected address at serial output miso. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set reset to ?1?. tu r n v cc power off. table 30-11. minimum wait delay before writing the next flash or eeprom location symbol minimum wait delay t wd_flash 4.5 ms t wd_eeprom 4.0 ms t wd_erase 4.0 ms t wd_fuse 4.5 ms 214 8042a?avr?07/09 atmega16hvb/32hvb 30.6.2 serial programming instruction set table 30-12 on page 214 and figure 30-2 on page 215 describes the instruction set. notes: 1. not all instructions are applicable for all parts. 2. a = address 3. bits are programmed ?0?, unprogrammed ?1?. 4. to ensure future compatibility, unused fuses and lock bits should be unprogrammed (?1?) . 5. refer to the corresponding section for fuse and lock bits, calibration and signature bytes and page size. 6. instructions accessing program memory use word addres s. this address may be random within the page range. 7. see htt://www.atmel.com/avr for application notes regarding programming and programmers. table 30-12. serial programming instruction set instruction/operation instruction format byte 1 byte 2 byte 3 byte4 programming enable $ac $53 $00 $00 chip erase (program memory/eeprom) $ac $80 $00 $00 poll rdy/bsy $f0 $00 $00 data byte out load instructions load extended address byte (1) $4d $00 extended adr $00 load program memory page, high byte $48 adr msb adr lsb high data byte in load program memory page, low byte $40 adr msb adr lsb low data byte in load eeprom memory page (page access) $c1 adr msb adr lsb data byte in read instructions read program memory, high byte $28 adr msb adr lsb high data byte out read program memory, low byte $20 adr msb adr lsb low data byte out read eeprom memory $a0 adr msb adr lsb data byte out read lock bits $58 $00 $00 data byte out read signature byte $30 $00 adr lsb data byte out read fuse bits $50 $00 $00 data byte out read fuse high bits $58 $08 $00 data byte out read extended fuse bits $50 $08 $00 data byte out read calibration byte $38 $00 $00 data byte out write instructions (6) write program memory page $4c adr msb adr lsb $00 write eeprom memory $c0 adr msb adr lsb data byte in write eeprom memory page (page access) $c2 adr msb adr lsb $00 write lock bits $ac $e0 $00 data byte in write fuse bits $ac $a0 $00 data byte in write fuse high bits $ac $a8 $00 data byte in write extended fuse bits $ac $a4 $00 data byte in 215 8042a?avr?07/09 atmega16hvb/32hvb if the lsb in rdy/bsy data byte out is ?1?, a pr ogramming operation is still pending. wait until this bit returns ?0? before the ne xt instruction is carried out. within the same page, the low data byte must be loaded prior to the high data byte. after data is loaded to the page buf fer, program the eeprom page, see figure 30-2 on page 215 . figure 30-2. serial programming instruction example byte 1 byte 2 byte 3 byte 4 adr lsb bit 15 b 0 serial programming instruction program memory/ eeprom memory page 0 page 1 page 2 page n-1 page buffer write program memory page/ write eeprom memory page load program memory page (high/low byte)/ load eeprom memory page (page access) byte 1 byte 2 byte 3 byte 4 bit 15 b 0 adr msb page offset page number ad r m ms sb a a adr r l lsb b 216 8042a?avr?07/09 atmega16hvb/32hvb 30.7 parallel programming this section describes parameters, pin mapping, and commands used to parallel program and verify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the atmega16hvb/32hvb. pulses are assumed to be at least 250 ns unless otherwise noted. 30.7.1 considerations for efficient programming the loaded command and address are retained in the device during programming. for efficient programming, the following should be considered. ? the command needs only be loaded once when writing or reading multiple memory locations. ? skip writing the data value 0xff, that is the contents of the entire eeprom (unless the eesave fuse is programmed) and flash after a chip erase. address high byte needs only be loaded before programming or reading a new 256 word window in flash or 256 byte eeprom. this considerat ion also applies to si gnature bytes reading. 30.7.2 signal names in this section, some pins of the atmega16hvb/32hvb are referenced by signal names describing their functionality during parallel programming, see figure 30-3 on page 216 and table 30-13 on page 217 . pins not described in the following table are referenced by pin names. the xa1/xa0 pins determine the action executed when the xtal1 pin is given a positive pulse. the bit coding is shown in table 30-15 on page 217 . when pulsing wr or oe , the command loaded determines the action executed. the different commands are shown in table 30-16 on page 218 . table 32-18 on page 239 shows the parallel programming characteristics. figure 30-3. parallel programming v cc +3.0 - 3.3 v g n d data[7:0] v fet (0 v ) +11.5 - 12.5 v reset pagel bs2 bs1 x1 x0 oe xtal1 w r rdy/bsy 217 8042a?avr?07/09 atmega16hvb/32hvb table 30-13. pin name mapping signal name in programming mode pin name i/o function rdy/bsy pa 0 o 0: device is busy programming 1: device is ready for new command. bs1 pa1 i byte select 1 (?0? selects low byte, ?1? selects high byte). bs2 pa2 i byte select 2 (?0? selects lo w byte, ?1? selects 2?nd high byte). pagel pa3 i program memory and eeprom data page load. reset reset i data pb7:0 i/o bi-directional data bus (output when oe is low). wr pc0 i write pulse (active low) oe pc1 i output enable (active low). xtal pc2 i xa0 pc3 i xtal action bit 0 xa1 pc4 i xtal action bit 1 table 30-14. pin values used to enter programming mode pin symbol value pb3 prog_enable[3] 0 pb2 prog_enable[2] 0 pb1 prog_enable[1] 0 pb0 prog_enable[0] 0 table 30-15. xa1 and xa0 coding xa1 xa0 action when xtal1 is pulsed 00 load flash or eeprom address (high or low address byte determined by bs1). 0 1 load data (high or low data byte for flash determined by bs1). 1 0 load command 1 1 no action, idle 218 8042a?avr?07/09 atmega16hvb/32hvb 30.7.3 enter programming mode the following algorithm puts the devi ce in parallel programming mode: 1. make sure the chip is started as explained in ?power-on reset and charger connect? on page 43 . 2. set reset to ?0? and toggle xtal1 at least six times. 3. set the prog_enable pins listed in table 30-14 on page 217 to ?0000? and wait at least 100 ns. 4. apply 11.5 - 12.5v to reset . any activity on prog_enable pins within 100 ns after +12v has been applied to reset , will cause the device to fail entering programming mode. 5. wait at least 50 s before sending a new command. 30.7.4 chip erase the chip erase will erase the flash and eeprom (1) memories plus lock bits. the lock bits are not reset until the program memory has been completely erased. the fuse bits are not changed. a chip erase must be perfor med before the flas h and/or eeprom are reprogrammed. note: 1. the eeprpom memory is preserved duri ng chip erase if the eesave fuse is programmed. load command ?chip erase? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?1000 0000?. this is the command for chip erase. 4. give xtal1 a positive pulse. this loads the command. 5. give wr a negative pulse. this starts the chip erase. rdy/bsy goes low. 6. wait until rdy/bsy goes high before loading a new command. table 30-16. command byte bit coding command byte command executed 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 0001 0001 write eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom 219 8042a?avr?07/09 atmega16hvb/32hvb 30.7.5 programming the flash the flash is organized in pages, see table 30-7 on page 211 . when programming the flash, the program data is latched into a page buffer. this allows one page of program data to be pro- grammed simultaneously. the following procedure describes how to program the entire flash memory: a. load command ?write flash? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?0001 0000?. this is the command for write flash. 4. give xtal1 a positive pulse. this loads the command. b. load address low byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?0?. this selects low address. 3. set data = address low byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address low byte. c. load data low byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data low byte (0x00 - 0xff). 3. give xtal1 a positive pulse. this loads the data byte. d. load data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?01?. this enables data loading. 3. set data = data high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the data byte. e. latch data 1. set bs1 to ?1?. this selects high data byte. 2. give pagel a positive pulse. this latches the data bytes. (see figure 30-5 for signal waveforms) f. repeat b through e until the entire buffer is filled or until all data within the page is loaded. while the lower bits in the address are mapped to words within the page, the higher bits address the pages within the flash . this is illustrated in figure 30-4 on page 220 . note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a page write. g. load address high byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?1?. this selects high address. 3. set data = address high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address high byte. 220 8042a?avr?07/09 atmega16hvb/32hvb h. program page 1. give wr a negative pulse. this starts programming of the entire page of data. rdy/bsy goes low. 2. wait until rdy/bsy goes high (see figure 30-5 for signal waveforms). i. repeat b through h until the entire flash is programmed or until all data has been programmed. j. end page programming 1. 1. set xa1, xa0 to ?10?. this enables command loading. 2. set data to ?0000 0000?. this is the command for no operation. 3. give xtal1 a positive pulse. this loads the command, and the internal write signals are reset. figure 30-4. addressing the flash which is organized in pages (1) note: 1. pcpage and pcword are listed in table 30-7 on page 211 . program memory word address within a page page address within the flash instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter 221 8042a?avr?07/09 atmega16hvb/32hvb figure 30-5. programming the flash waveforms (1) note: 1. ?xx? is don?t care. the letters re fer to the programming description above. 30.7.6 programming the eeprom the eeprom is organized in pages, see table 30-8 on page 211 . when programming the eeprom, the program data is latche d into a page buffer. this al lows one page of data to be programmed simultaneously. th e programming algorithm for th e eeprom data memory is as follows (refer to ?programming the flash? on page 219 for details on command, address and data loading): 1. a: load command ?0001 0001?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. c: load data (0x00 - 0xff). 5. e: latch data (give pagel a positive pulse). k: repeat 3 through 5 until the entire buffer is filled. l: program eeprom page 1. set bs to ?0?. 2. give wr a negative pulse. this starts prog ramming of the eeprom page. rdy/bsy goes low. 3. wait until to rdy/bsy goes high before programming the next page (see figure 30-6 for signal waveforms). rdy/bsy wr oe reset +12v pagel bs2 0x10 addr. low addr. high data data low data high addr. low data low data high xa1 xa0 bs1 xtal1 xx xx xx abcdeb cdegh f 222 8042a?avr?07/09 atmega16hvb/32hvb figure 30-6. programming the eeprom waveforms 30.7.7 reading the flash the algorithm for reading the flash memory is as follows (refer to ?programming the flash? on page 219 for details on command and address loading): 1. a: load command ?0000 0010?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the flash word low byte can now be read at data. 5. set bs to ?1?. the flash word high byte can now be read at data. 6. set oe to ?1?. 30.7.8 reading the eeprom the algorithm for reading the eeprom memory is as follows (refer to ?programming the flash? on page 219 for details on command and address loading): 1. a: load command ?0000 0011?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the eeprom data byte can now be read at data. 5. set oe to ?1?. rdy/bsy wr oe reset +12v pagel bs2 0x11 addr. high data addr. low data addr. low data xx xa1 xa0 bs1 xtal1 xx agbceb c el k 223 8042a?avr?07/09 atmega16hvb/32hvb 30.7.9 programming the fuse low bits the algorithm for programming the fuse low bits is as follows (refer to ?programming the flash? on page 219 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. give wr a negative pulse and wait for rdy/bsy to go high. 30.7.10 programming the fuse high bits the algorithm for programming the fuse high bits is as follows (refer to ?programming the flash? on page 219 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs1 to ?1? and bs2 to ?0?. this selects high data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs1 to ?0?. this selects low data byte. figure 30-7. programming the fuses waveforms 30.7.11 programming the lock bits the algorithm for programming the lock bits is as follows (refer to ?programming the flash? on page 219 for details on command and data loading): 1. a: load command ?0010 0000?. 2. c: load data low byte. bit n = ?0? programs the lock bit. if lb mode 3 is programmed (lb1 and lb2 is programmed), it is not possible to program the boot lock bits by any external programming mode. 3. give wr a negative pulse and wait for rdy/bsy to go high. the lock bits can only be cleared by executing chip erase. rdy/bsy wr oe reset +12v pagel 0x40 data data xx xa1 xa0 bs1 xtal1 ac 0x40 data xx ac write fuse low byte write fuse high byte 0x40 data xx ac write extended fuse byte bs2 224 8042a?avr?07/09 atmega16hvb/32hvb 30.7.12 reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to ?programming the flash? on page 219 for details on command loading): 1. a: load command ?0000 0100?. 2. set oe to ?0?, bs2 to ?0? and bs1 to ?0?. the status of the fuse low bits can now be read at data (?0? means programmed). 3. set oe to ?0?, bs2 to ?1? and bs1 to ?1?. the status of the fuse high bits can now be read at data (?0? means programmed). 4. set oe to ?0?, bs2 to ?0? and bs1 to ?1?. the status of the lock bits can now be read at data (?0? means programmed). 5. set oe to ?1?. figure 30-8. mapping between bs1, bs2 and the fuse and lock bits during read 30.7.13 reading the signature bytes the algorithm for reading the signatur e bytes is as follows (refer to ?programming the flash? on page 219 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte (0x00 - 0x02). 3. set oe to ?0?, and bs to ?0?. the selected signature byte can now be read at data. 4. set oe to ?1?. 30.7.14 reading the calibration byte the algorithm for reading the calibration byte is as follows (refer to ?programming the flash? on page 219 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte, 0x00. 3. set oe to ?0?, and bs1 to ?1?. the calibration byte can now be read at data. 4. set oe to ?1?. lock bits 0 1 bs2 fuse high byte 0 1 bs1 data fuse low byte 0 1 bs2 extended fuse byte 225 8042a?avr?07/09 atmega16hvb/32hvb 31. operating circuit figure 31-1. operating circuit r8 r6 d6 d7 d8 d9 d10 r31 atmega16hvb/32hvb vfet oc pvt od + pv4 pv3 pv2 pv1 nv pa1/adc1/sgnd pa0/adc0/sgnd reset vreg pb7 pb6 pb3 pb4 pb5 batt r7 vref vrefgnd smbdata smbclk r28 r29 vcc r20 r19 r21 pa2 pc5 r27 pb0 pb1/ckout pb2 pc3/sda pc4/scl pc0/ext_prot d3 r22 r23 pc2 r17 c14 c13 c15 pc1 c7 c6 c5 r5 c16 c12 sw1 d4 sys present r24 fuse blow fuse status r25 r26 f1 d1 r16 q2 q3 q4 pa3 r9 r10 r11 r12 c9 pi ni nni ppi r13 r14 r18 - r3 r1 r2 r4 s-8244 r15 sense vc1 vc2 vc3 vss vcc ict co c8 vcc vcc vcc vcc c10 c4 c3 c2 c1 c11 r30 c17 q1 d2 d5 r33 r32 cell4 cell3 cell2 cell1 pack+ pack- c18 vclmp10 optional secondary protection and fuse blow circuitry 226 8042a?avr?07/09 atmega16hvb/32hvb table 31-1. bill of materials symbol number description c1-c4, c10, c11 6 capacitor, ceramic, 0.1 - 1.0 f, 50v, x7r c5-c8 4 capacitor, ceramic, 0.01 - 0.5 f, 50v, x7r c9, c12, c13, c15 4 capacitor, ceramic, 0.1 f, 50v, x7r c14 1 capacitor, ceramic, 2.2 - 4.7 f, 10v, x7r c16 1 capacitor, ceramic, 1 - 22 f, 10v, x7r c17 1 capacitor, ceramic, 0.47 f, 10v, x7r c18 1 capacitor, cerami c, 22 nf, 50v, x7r d1 1 diode, signal d2 1 diode, double, shottky d4 1 diode, signal d3 1 diode, zener, value from design considerations d4 1 diode, zener, 5v6 d5 1 diode, double, zener, 5v6 d6-d10 5 leds f1 1 chemical fuse q1 1 n-fet, 50v, 0.22a q2, q3 2 n-fet, 30v, 10a q4 1 n-fet, 20v, 1.3a r1-r4 4 resistor, chip, 1-10 k , 1/16w, 5% r5-r9 5 resistor, chip, 10-1000 , 1/16w, 5% r10 1 sense resistor, 1-10 m , 1w, 1% r11, r12 2 resistor, chip, 10-500 , 1/16w, 5% r13, r14, r18, r19, r20, r21, r25 7 resistor, chip 1 k , 1/16w, 5% r15 1 resistor, chip, 100-1000 , 1/16w, 5% r16, r17 2 resistor, chip 200 k , 1/16w, 5% r22 1 resistor, value from design considerations r23 1 resistor, value from design considerations r24 1 resistor, chip 1 k , 1/16w, 5% r26, r27 2 resistor, chip 100 , 1/16w, 5% r28, r29 2 resistor, chip 1 m , 1/16w, 5% r30 1 resistor, chip 820 , 1/16w, 5% r31 1 resistor, chip 10 k , 1/16w, 5% r32, r33 2 ntc thermistor, 10 k , b = 3000 - 4000 227 8042a?avr?07/09 atmega16hvb/32hvb sw 1 switch, push button u1 1 atmega32hvb (atmel) u2 1 s-8244 secondary protection device (seiko instruments) table 31-1. bill of materials symbol number description 228 8042a?avr?07/09 atmega16hvb/32hvb 32. electrical characteristics 32.1 absolute maximum ratings* 32.2 supply current characteristics operating temperature.................................... -40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c voltage on pa0 - pa3, pi, ni, ppi and nni with respect to ground ............................. -0.5v to v reg +0.5v voltage on pb0 - pb7 with respect to ground ............... .............. -0.5v to vcc +0.5v voltage on pc0 - pc4, pv1, and nv with respect to ground................-0.5v to + 6.0v voltage on pc5, batt, pvt, vfet, oc, od, pv4, pv3, and pv2 with respect to ground........................-0.5v to + 35v voltage on vclmp10 and reset with respect to ground ......................................-0.5v to + 13v maximum operating voltage on vreg and vcc............. 4.5v maximum operating voltage on vfet .............................. 25v table 32-1. t a = 25c unless otherwise noted. symbol parameter condition min typ max unit i vfet active current vfet=16v, cpu clock=8mhz, all prr bits set 3.75 5 ma vfet=16v, cpu clock=1mhz, all prr bits set 760 1000 a idle current vfet=16v, cpu clock=1mhz, all prr bits set 215 293 adcnrm current vfet=16v, cpu clock=1mhz, all prr bits except prvadc are set, vadc enabled. 350 power-save current vfet=16v, only wdt enabled, duvr mode disabled. 28 46 vfet=16v, wdt, cc-adc, oc, od and battery protection enabled, duvr mode disabled. 85 138 power-off current vfet=6v <1 2 229 8042a?avr?07/09 atmega16hvb/32hvb 32.3 nfet driver characteristics note: the nfet drivers require a minimum total cell voltage of 6v or higher or a charger connected to turn-on the fets. note tha t this limit only applies if the fet is disabled in advanced. if the fet is already enabled, the fet will be fully operational in the entire voltage range of the device (4-25v). table 32-2. t a = 25c unless otherwise noted. symbol parameter condition min. typ. max. units v oc,on oc pin on voltage relative to pvt voltage oc enabled, vfet=16v 13 v oc enabled, vfet=10v 13 oc enabled, vfet=4v 6 v od,on od pin on voltage relative to batt voltage od enabled, vfet=16v 13 od enabled, vfet=10v 13 od enabled, vfet=4v 6 v oc,off oc pin off voltage realtive to gnd 0.0 v od,off od pin off voltage realtive to gnd 0.0 t r,oc rise time on oc pin v (oc-pvt) =0 to 2v, c eq =4.7nf, vfet=16v 0.8 ms v (oc-pvt) =0 to 2v, c eq =4.7nf, vfet=10v 1.1 v (oc-pvt) =0 to 2v, c eq =4.7nf, vfet=6v 3 v (oc-pvt) =2 to 4v, c eq =4.7nf, vfet=16v 1 v (oc-pvt) =2 to 4v, c eq =4.7nf, vfet=10v 1.2 v (oc-pvt) =2 to 4v, c eq =4.7nf, vfet=6v 1.3 t r,od rise time on od pin v (od-batt) =0 to 2v, c eq =4.7nf, vfet=16v 0.8 v (od-batt) =0 to 2v, c eq =4.7nf, vfet=10v 1.1 v (od-batt) =0 to 2v, c eq =4.7nf, vfet=6v 3 v (od-batt) =2 to 4v, c eq =4.7nf, vfet=16v 1 v (od-batt) =2 to 4v, c eq =4.7nf, vfet=10v 1.2 v (od-batt) =2 to 4v, c eq =4.7nf, vfet=6v 1.3 t f,oc fall time on oc pin v (od-pvt) =v oc,on to 0v 50 ns t f,od fall time on od pin v (od-batt) =v od,on to 0v 50 v vfet,duvr regulated vfet voltage in duvr mode duvr enabled, vref=1.1v 4.1 4.9 v 230 8042a?avr?07/09 atmega16hvb/32hvb 32.4 reset characteristics notes: 1. the voltage at the pack + terminal will be slightly higher than v pot when the chip is enabled. this is because of an internal pull-down current on the batt pin in the range 50 - 150 ua and the r batt resistor connected between the pack + terminal and the batt pin. r batt = 1k gives a voltage drop 0.05 - 0.15v. 2. the power-on reset will not work unless the voltage has been below v pot (falling) after a power-off condition. 32.5 voltage regulator characteristics 32.6 voltage reference and temper ature sensor characteristics notes: 1. calibration is done in atmel factory test. software shou ld calibrate the vref by writing the bgcrr and bgccr registers with the calibration values stored in the signature row. 2. this value is not tested in production. table 32-3. t a = -40 to 85c unless otherwise noted. symbol parameter condition min typ max units v pot power-on threshold voltage (rising) (1) 4.5 7 v power-on threshold voltage (falling) (1)(2) 4.5 6.3 t rst minimum pulse width on reset pin 900 ns v bot brown-out detection (bod) trigger level t a = 25c 2.9 v v hyst bod level hysteresis t a = 25c 50 mv table 32-4. t a = -40 to 85c unless otherwise noted. symbol parameter condition min typ max unit v vreg regulator output voltage vfet=16.8v, i out =20ma 3.1 v vfet=6v, i out =20ma 3.1 vfet=4v, i out =7ma 3.1 v rscl voltage regulator short- circuit level at vfet pin 3.3 3.7 v blod voltage regulator black-out detection level at vreg pin t a = 25c 2.65 table 32-5. t a = -40 to 85c unless otherwise noted. parameter condition min typ max unit reference voltage 1.100 v ref. voltage accuracy (1) after factory calibration, t a = 25c 0.1 0.2 % temperature drift (1)(2) t a = -40 - 85 c6090 ppm/k t a = 0 - 60 c2550 vref calibration hold off time creg=2.2f, bgccr write 2 s creg=2.2f, bgcrr write 5 v ptat , voltage proportional to absolute temperature (2) 0.6 mv/k v ptat absolute accuracy (3) 5 k 231 8042a?avr?07/09 atmega16hvb/32hvb 3. the measured v ptat voltage must be scaled with the calibration value stored in the v ptat calibration register to get the absolute temperature. the design target accuracy for this parameter assumes an exact calibration temperature. actual accuracy of this parameter after calibration in atmel factory test remains to be determined. 32.7 adc characteristics 32.7.1 voltage adc characteristics notes: 1. value is after atmel factory offset and gain compensation in production (for details, see table 29-3, ?signature row addressing.,? on page 199 ) and it includes drift over the whole temperature range. 2. value not tested in production but guarantied by design and characterization. table 32-6. t a = -40 to 85c unless otherwise noted. parameter condition min typ max unit conversion time clk vadc = 1 mhz 519 s resolution 12 bits gain adc0/1 (un-scaled) 263 v/lsb gain cell inputs (x0.2) 1.42 mv/lsb inl (2) adc0, adc1 1 3 lsb cell1, cell2, cell3 1 3 cell4 2 5 input voltage range adc0, adc1, vtemp 0 1 v input voltage range cell1 1.8 5 input voltage range cell2 v pv1-gnd >1.8v 0 5 input voltage range cell3 v pv2-gnd >1.8v 0 5 input voltage range cell4 v pv3-gnd >1.8v 0 5 offset drift (1)(2) adc0, adc1 1 lsb cell1, cell2, cell3 1 cell4 5 gain drift (1)(2) adc0, adc1 6 lsb cell1, cell2, cell3 7 cell4 15 232 8042a?avr?07/09 atmega16hvb/32hvb 32.7.2 coulomb counter adc characteristics notes: 1. values based on characterization data. 2. after software offset compensation, using the polarity switching (cadpol) feature. 3. value includes drift over the whole temperature range. 32.8 clock characteristics notes: 1. the frequency is stored in the value after factory calibration at 85oc 2. value not tested in production, but it is guarantied by design and characterization over the whole temperature range. 3. the actual oscillator frequency is measured in production and stored in the device signature row (for details, see ?reading the signature row from software? on page 199 ). table 32-7. t a = -40 to 85c unless otherwise noted. parameter condition min typ max unit conversion time instantaneous conversion, clk cc-adc =32khz 3.9 ms accumulated conversion cadas=11, clk cc-adc =32khz 1 s resolution instantaneous conversion 13 bits accumulated conversion 18 gain accumulated conversion, cadvse=0 1.67 v/lsb accumulated conversion, cadvse=1 0.84 instantaneous conversion, cadvse=0 53.7 instantaneous conversion, cadvse=1 26.9 input voltage range cadvse = 0 -200 200 mv cadvse = 1 -100 100 inl (1) t a = 0 - 60 c 0.005 0.003 % fsr offset error (2) accumulated conversion, t a = 25 c-7v offset error drift (1)(2) accumulated conversion 30 nv/ c gain error (1)(3) 0.4 1 % gain error drift (1) 0.1 table 32-8. t a = -40 to 85c unless otherwise noted. parameter condition min typ max unit calibrated fast rc oscillator frequency after factory calibration at t a =25 c 7.92 8 8.08 mhz frequency drift (2) with run-time calibration with osi interface and slow rc oscillator as calibration clock 3% slow rc oscillator (1) frequency (3) 91 131 171 khz frequency drift 1 % frequency prediction error 0.5 ultra low power rc oscillator (1) frequency (3) 89 128 167 khz frequency drift (2) 6% 233 8042a?avr?07/09 atmega16hvb/32hvb 32.9 cell balancing characteristic 32.10 battery protectio n characteristics notes: 1. value includes drift in the internal voltage reference after vref factory calibration. 2. levels in charge and discharge direction can be configured independent of each other. 32.11 external interrupt characteristics table 32-9. t a = 25c unless otherwise noted. parameter condition min typ max unit balancing current battery cell voltage v cell =4.2v, v-adc filter resistance=470 4ma table 32-10. t a = -40 to 85c unless otherwise noted. symbol parameter condition min typ max unit v scd =v nni -v ppi short circuit detection level accuracy (1)(2) v scd =20mv (min level) 14 20 26 mv v scd =150mv 130 150 170 v scd =310mv(max) 280 310 340 v cocd =v ppi -v nni , v docd =v nni -v ppi charge/discharge over current detection level accuracy (1)(2) v cocd,docd =20mv (min level) 15 20 25 v cocd,docd =150mv 130 150 170 v cocd,docd =310mv(max) 280 310 340 v chcd =v ppi -v nni , v dhcd =v nni -v ppi charge/discharge high current detection detection level accuracy (1)(2) v chcd,dhcd =20mv (min level) 15 20 25 v chcd,dhocd =150mv 130 150 170 v chcd,dhcd =310mv(max) 280 310 340 table 32-11. asynchronous external interrupt characteristics symbol parameter condition min typ max units t int minimum pulse width for asynchronous external interrupt 50 ns 234 8042a?avr?07/09 atmega16hvb/32hvb 32.12 general i/o li nes characteristics 32.12.1 port a and b characteristics notes: 1. ?max? means the highest value where the pin is guaranteed to be read as low 2. ?min? means the lowest value where t he pin is guaranteed to be read as high 3. although each i/o port can sink more than the test conditions (5 ma at v cc = 3.3v) under steady stat e conditions (non-tran- sient), the following must be observed: - the sum of all iol should not exceed 20 ma. if iol exceeds the test condition, vol may exceed the related sp ecification. pins are not guar anteed to sink current greater than the listed test condition. 4. although each i/o port can source more than the test conditions (2 ma at v cc = 3.3v) under steady state conditions (non- transient), the following must be observed: - the sum of all ioh should not exceed 2 ma. 32.12.2 port c characteristics note: 1. this values is based on characterization and is not tested in production. table 32-12. t a = - 40 to 85 c, v cc = 3.3v (unless otherwise noted) symbol parameter condition min. typ. max. units v il input low voltage, except reset pin -0.5 0.3v cc (1) v v il1 input low voltage, reset pin 0.3v cc (1) v ih input high voltage, except reset pin 0.6v cc (2) v cc + 0.5 v ih1 input high voltage, reset pin 0.9v cc (2) v cc + 0.5 v ol output low voltage i ol = 5ma 0.5 v oh output high voltage i oh = 2 ma 2.3 i il input leakage current i/o pin pin low (absolute value) 1 a i ih input leakage current i/o pin pin high (absolute value) 1 r rst reset pull-up resistor 30 60 k r pu i/o pin pull-up resistor 20 50 table 32-13. pc0-pc4 characteristics symbol parameter condition min max units v il input low-voltage -0.5 0.8 v v ih input high-voltage 2.1 5.5 v ol (1) output low-voltage 350 a sink current 0 0.4 table 32-14. pc5 characteristic symbol parameter condition min max units v ol output low-voltage 500 a sink current 0 0.2 v 235 8042a?avr?07/09 atmega16hvb/32hvb 32.13 2-wire serial in terface characteristics table 32-15 on page 235 describes the requirements for devices connected to the two-wire serial bus. the atmega16hvb/32hvb two-wire serial interface meets or exceeds these requirements under the noted conditions. timing symbols refer to figure 32-1 on page 236 . notes: 1. in atmega16hvb/32hvb, this par ameter is characterized and not tested. 2. c b = capacitance of one bus line in pf. 3. f ck = cpu clock frequency 4. this requirement applies to all atmega16hvb/32hvb two-wire serial interface operation. other devices connected to the two-wire serial bus need only obey the general f scl requirement. table 32-15. two-wire serial bus requirements symbol parameter condition min max units v il input low-voltage -0.5 0.8 v v ih input high-voltage 2.1 5.5 v ol (1) output low-voltage 350 a sink current 0 0.4 tr (1) rise time for both sda and scl 300 ns tof (1) output fall time from v ihmin to v ilmax c b < 400 pf (2) 250 tsp (1) spikes suppressed by input filter 0 50 i i input current each i/o pin 0.1v bus < v i < 0.9v bus -5 5 a c i (1) capacitance for each i/o pin ? 10 pf f scl scl clock frequency f ck (3) > max(16f scl , 450 khz) (4) 0 100 khz rp value of pull-up resistor f scl 100 khz t hd;sta hold time (repeated) start condition f scl 100 khz 4.0 ? s t low low period of the scl clock f scl 100 khz 4.7 ? t high high period of the scl clock f scl 100 khz 4.0 ? t su;sta set-up time for a repeated start condition f scl 100 khz 4.7 ? t hd;dat data hold time f scl 100 khz 0.3 3.45 t su;dat data setup time f scl 100 khz 250 ? t su;sto setup time for stop condition f scl 100 khz 4.0 ? t buf bus free time between a stop and start condition f scl 100 khz 4.7 ? v bus 0,4v ? 350a ------------------------------- v bus 0,4v ? 100a ------------------------------- 236 8042a?avr?07/09 atmega16hvb/32hvb figure 32-1. two-wire serial bus timing 32.14 spi timing characteristics see figure 32-2 on page 237 and figure on page 237 for details. note: 1. refer to ?serial programming? on page 211 for serial programming requirements. t su;sta t low t high t low t of t hd;sta t hd;dat t su;dat t su;sto t buf scl sda t r table 32-16. spi timing parameters description mode min typ max units 1 sck period master see figure ns 2 sck high/low master 50% duty 3 rise/fall time master 3.6 4 setup master 10 5 hold master 10 6 out to sck master 0.5 ? t sck 7 sck to out master 10 8 sck to out high master 10 9ss low to out slave 15 10 sck period slave 4 ? t ck + 40 ns 11 sck high/low (1) slave 2 ? t ck + 20 ns 12 rise/fall time slave 1.6 s 13 setup slave 10 ns 14 hold slave t ck 15 sck to out slave 15 16 sck to ss high slave 20 17 ss high to tri-state slave 10 18 ss low to sck slave 20 237 8042a?avr?07/09 atmega16hvb/32hvb figure 32-2. spi interface timing requirements (master mode) spi interface timing requirements (slave mode) 32.15 serial programming characteristics figure 32-3. serial programming timing mo si (data output) sck (cpol = 1) mi so (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 61 22 3 45 8 7 mi so (data output) sck (cpol = 1) mo si (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 10 11 11 12 13 14 17 15 9 x 16 mosi miso sck t ovsh t shsl t slsh t shox t sliv 238 8042a?avr?07/09 atmega16hvb/32hvb figure 32-4. serial programming waveforms note: 1. 2.2 t clcl for f ck < 12 mhz, 3 t clcl for f ck >= 12 mhz 32.16 parallel programming characteristics figure 32-5. parallel programming timing, including some general timing requirements msb msb lsb lsb serial clock input (sck) serial data input (mosi) (miso) sample serial data output table 32-17. serial programming characteristics, t a = -40 c to 85 c, v cc = 3.3v (unless otherwise noted) symbol parameter min typ max units 1/t clcl oscillator frequency (atmega16hvb/32hvb) 0 8 mhz t clcl oscillator period (atmega16hvb/32hvb) 125 ns t shsl sck pulse width high 2.2 t clcl (1) t slsh sck pulse width low 2.2 t clcl (1) t ovsh mosi setup to sck high t clcl t shox mosi hold after sck high 2 t clcl t sliv sck low to miso valid 15 data & contol (data, xa0/1, bs1, bs2) xtal1 t xhxl t wlwh t dvxh t xldx t plwl t wlrh wr rdy/bsy pagel t phpl t plbx t bvph t xlwl t wlbx t bvwl wlrl 239 8042a?avr?07/09 atmega16hvb/32hvb figure 32-6. parallel programming timing, loading sequence with timing requirements (1) note: 1. the timing requirements shown in figure 32-5 (i.e., t dvxh , t xhxl , and t xldx ) also apply to load- ing operation. figure 32-7. parallel programming timing, reading sequence (within the same page) with timing requirements (1) note: 1. the timing requirements shown in figure 32-5 (i.e., t dvxh , t xhxl , and t xldx ) also apply to read- ing operation. table 32-18. parallel programming characteristics symbol parameter min typ max units v pp programming enable volt age (reset in put) 11.5 12.5 v i pp programming enable current 250 a t dvxh data and control valid before xtal1 high 67 ns t xlxh xtal1 low to xtal1 high 200 ns t xhxl xtal1 pulse width high 150 ns t xldx data and control hold after xtal1 low 67 ns xtal1 pagel t plxh xlxh t t xlph addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) load data (low byte) load data (high byte) load data load address (low byte) xtal1 oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) read data (low byte) read data (high byte) load address (low byte) t bvdv t oldv t xlol t ohdz 240 8042a?avr?07/09 atmega16hvb/32hvb notes: 1. t wlrh is valid for the write flash, write eepro m, write fuse bits and write lock bits commands. 2. t wlrh_ce is valid for the chip erase command t xlwl xtal1 low to wr low 0 ns t xlph xtal1 low to pagel high 0 t plxh pagel low to xtal1 high 150 t bvph bs1 valid before pagel high 67 t phpl pagel pulse width high 150 t plbx bs1 hold after pagel low 67 t wlbx bs2/1 hold after wr low 67 t plwl pagel low to wr low 67 t bvwl bs1 valid to wr low 67 t wlwh wr pulse width low 150 t wlrl wr low to rdy/bsy low 0 1 s t wlrh wr low to rdy/bsy high (1) 3.7 4.5 ms t wlrh_ce wr low to rdy/bsy high for chip erase (2) 7.5 9 t xlol xtal1 low to oe low 0 ns t bvdv bs1 valid to data valid 0 250 t oldv oe low to data valid 250 t ohdz oe high to data tri-stated 250 table 32-18. parallel programming characteristics (continued) symbol parameter min typ max units 241 8042a?avr?07/09 atmega16hvb/32hvb 33. typical characteristics all typical characteristics contained in this data sheet are based on characterization of atmega16/32hvb. 33.1 supply current characteristics 33.1.1 active supply current characteristics active mode current measurements with all bi ts in the prr registers set and all i/o modules turned off. figure 33-1. active supply current vs. v vfet , internal rc oscillator, 8 mhz. figure 33-2. active supply current vs. v vfet , internal rc oscillator, 4 mhz. 8 5 c 25 c -40 c 3.6 3.65 3.7 3.75 3. 8 3. 8 5 3.9 3.95 4 46 8 10 12 14 16 1 8 20 v v fet [ v ] i [ma] v fet 8 5 c 25 c -40 c 2.2 2.24 2.2 8 2.32 2.36 2.4 2.44 46 8 10 12 14 16 1 8 20 v v fet [ v ] i [ma] v fet 242 8042a?avr?07/09 atmega16hvb/32hvb figure 33-3. active supply current vs. v vfet , internal rc oscillator, 2 mhz. figure 33-4. active supply current vs. v vfet , internal rc oscillator, 1 mhz. 8 5 c 25 c -40 c 1.21 1.23 1.25 1.27 1.29 1.31 1.33 46 8 10 12 14 16 1 8 20 v v fet [ v ] i [ma] v fet 8 5 c 25 c -40 c 0.72 0.73 0.74 0.75 0.76 0.77 0.7 8 0.79 0. 8 46 8 10 12 14 16 1 8 20 v v fet [ v ] i [ma] v fet 243 8042a?avr?07/09 atmega16hvb/32hvb 33.1.2 idle supply current characteristics idle current consumption measurements with all bits in the prr registers set and all i/o modules are turned off. figure 33-5. idle supply current vs. v vfet , internal rc oscillator, 8 mhz. figure 33-6. idle supply current vs. v vfet , internal rc oscillator, 4 mhz. 8 5 c 25 c -40 c 0.675 0.695 0.715 0.735 0.755 0.775 0.795 0. 8 15 46 8 10 12 14 16 1 8 20 v v fet [ v ] i [ma] v fet 8 5 c 25 c -40 c 0.42 0.43 0.44 0.45 0.46 0.47 0.4 8 46 8 10 12 14 16 1 8 20 v v fet [ v ] i [ma] v fet 244 8042a?avr?07/09 atmega16hvb/32hvb figure 33-7. idle supply current vs. v vfet , internal rc oscillator, 2 mhz. figure 33-8. idle supply current vs. v vfet , internal rc oscillator, 1 mhz. 8 5 c 25 c -40 c 0.2 8 0.2 8 4 0.2 88 0.292 0.296 0.3 0.304 0.30 8 46 8 10 12 14 16 1 8 20 v v fet [ v ] i [ma] v fet 8 5 c 25 c -40 c 0.205 0.209 0.213 0.217 0.221 0.225 46 8 10 12 14 16 1 8 20 v v fet [ v ] i [ma] v fet 245 8042a?avr?07/09 atmega16hvb/32hvb 33.1.3 power-save current characteristics power-save current consumption with external interrupt and smbus connect/disconnect func- tionality enabled. the watchdog timer, cc-adc, current battery protection (cbp), vref, and oc/od are disabled. figure 33-9. power-save suppl y current vs. v vfet , external interrupt and smbus enabled, all other modules disabled. table 33-1 shows additional current consumption that needs to be added to the total power-bud- get when additional modules are enableds. note: 1. default i/o register configurat ion used. ppi and nni connected to gnd. 2. measurements done with fairchild fds6690a n-channel mosfet. table 33-1. typical additional i/o modules current consumption in power-save i/o modules enabled typical current consumption wdt vref cbp (1) cc/od (2) cc-adc (t a =25c and v vfet =12v) x 0.8 a x x 12 a xxxx 41 a xxxxx55 a 8 5 c 25 c -40 c 17 19 21 23 25 27 29 31 33 35 46 8 10 12 14 16 1 8 20 v v fet [ v ] i [ u a] v fet 246 8042a?avr?07/09 atmega16hvb/32hvb 33.1.4 power-off current characteristics figure 33-10. power-off supply current vs. v vfet 33.2 nfet driver characteristics 33.2.1 oc/od levels figure 33-11. oc/od pin voltage vs. v vfet 8 5 c 25 c -40 c 0.6 0. 8 1 1.2 1.4 1.6 1. 8 46 8 10 12 14 16 1 8 20 v v fet [ v ] i [ u a] v fet 8 5 c 25 c -40 c 6 8 10 12 14 16 1 8 v v fet [ v ] 10 15 20 25 30 35 pin v oltage [ v ] 247 8042a?avr?07/09 atmega16hvb/32hvb 33.2.2 oc/od rise time from 0v to 2v gate-source voltage with 4.7nf load figure 33-12. oc/od rise time, v gs = 0 to 2v vs. v vfet 33.2.3 oc/od rise time from 2v to 4v gate-source voltage with 4.7nf load figure 33-13. oc/od rise time, v gs = 2 to 4v vs. v vfet 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 time [ms] 6 8 10 12 14 16 1 8 v v fet [ v ] 70 c 25 c 0 0.5 1 1.5 2 2.5 3 time [ ms ] 6 8 10 12 14 16 1 8 v v fet [ v ] 70 c 25 c 248 8042a?avr?07/09 atmega16hvb/32hvb 33.3 battery protection characteristics figure 33-14. battery protection level 33.4 clock characteristics 33.4.1 fast rc oscillator characteristics figure 33-15. fast rc oscillator frequency vs. te mperature (after factory calibration) 10 60 110 160 210 260 310 [m v ] detection le v el max typ(25 c) f3 f4 f5 f6 f7 f 8 f9 fa fb fc fd 77 7 8 79 7a 7b 7c 7d 37 3 8 39 3a 3b 3c 3d 17 min register v al u e 7.75 7. 8 7. 8 5 7.9 7.95 8 8 .05 8 .1 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] [mhz] fre qu ency 249 8042a?avr?07/09 atmega16hvb/32hvb figure 33-16. calibrated fast rc oscillator frequency vs. osccal value. 33.4.2 ultra low power rc oscillator characteristics figure 33-17. ulp rc oscillator freq uency vs. temperature 25 ?c 16 14 12 10 8 6 4 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 osccal value f rc (m hz) 105 106 107 10 8 109 110 111 112 113 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] fre qu ency [khz] 250 8042a?avr?07/09 atmega16hvb/32hvb 33.4.3 slow rc oscillator characteristics figure 33-18. slow rc oscillator freq uency vs. temperature 33.5 voltage reference characteristics figure 33-19. typical vref curve with atmel factory calibration at 25c and 85c. 117.6 117.7 117. 8 117.9 11 8 11 8 .1 11 8 .2 11 8 .3 11 8 .4 11 8 .5 11 8 .6 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] fre qu ency [khz] temperat u re [c] -40 -2 0 0 20 40 60 8 0 1.091 1.092 1.093 1.094 1.095 1.096 1.097 1.09 8 1.099 1.100 1.101 v ref [ v ] 251 8042a?avr?07/09 atmega16hvb/32hvb figure 33-20. typical vref deviation curve with atmel factory calibration at 25c and 85c. 33.6 voltage regulator characteristics figure 33-21. voltage regulator vs. v vfet , i load = 10 ma. 8 5 c 25 c -40 c 3.21 3.22 3.23 3.24 3.25 3.26 3.27 46 8 10 12 14 16 1 8 20 22 24 26 v v fet [ v ] v reg [ v ] 252 8042a?avr?07/09 atmega16hvb/32hvb figure 33-22. voltage regulator vs. v vfet , i load = 20 ma. figure 33-23. voltage regulator short-circuit level at v vfet pin vs. temperature. 8 5 c 25 c -40 c 2.4 2.5 2.6 2.7 2. 8 2.9 3 3.1 3.2 3.3 46 8 10 12 14 16 1 8 20 22 24 26 v v fet [ v ] v reg [ v ] 3.45 3.5 3.55 3.6 3.65 3.7 3.75 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] v rscl [ v ] rising falling 253 8042a?avr?07/09 atmega16hvb/32hvb figure 33-24. blod level. 33.7 bod threshold characteristics figure 33-25. bod level. 2.637 2.639 2.641 2.643 2.645 2.647 2.649 2.651 2.653 2.655 2.657 2.659 2.661 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] v blod [ v ] falling rising 2. 8 2 2. 8 4 2. 8 6 2. 88 2.9 2.92 2.94 2.96 2.9 8 3 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 090 temperat u re [c] v cc [ v ] 254 8042a?avr?07/09 atmega16hvb/32hvb 34. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved ? ? ? ? ? ? ? ? (0xfe) bpplr ? ? ? ? ? ? bpple bppl 140 (0xfd) bpcr ? ? epid scd docd cocd dhcd chcd 141 (0xfc) bphctr ? ? hcpt[5:0] 143 (0xfb) bpoctr ? ? ocpt[5:0] 142 (0xfa) bpsctr ? scpt[6:0] 142 (0xf9) bpchcd chcdl[7:0] 145 (0xf8) bpdhcd dhcdl[7:0] 145 (0xf7) bpcocd cocdl[7:0] 145 (0xf6) bpdocd docdl[7:0] 144 (0xf5) bpscd scdl[7:0] 144 (0xf4) reserved ? ? ? ? ? ? ? ? (0xf3) bpifr ? ? ? scif docif cocif dhcif chcif 147 (0xf2) bpimsk ? ? ? scie docie cocie dhcie chcie 146 (0xf1) cbcr ? ? ? ? cbe4 cbe3 cbe2 cbe1 155 (0xf0) fcsr ? ? ? ? duvrd cps dfe cfe 153 (0xef) reserved ? ? ? ? ? ? ? ? (0xee) reserved ? ? ? ? ? ? ? ? (0xed) reserved ? ? ? ? ? ? ? ? (0xec) reserved ? ? ? ? ? ? ? ? (0xeb) reserved ? ? ? ? ? ? ? ? (0xea) cadrdc cadrdc[7:0] 115 (0xe9) cadrcc cadrcc[7:0] 115 (0xe8) cadcsrc - - - - - - - cadvse 114 (0xe7) cadcsrb ? cadacie cadrcie cadicie ? cadacif cadrcif cadicif 112 (0xe6) cadcsra caden cadpol cadub cadas[1:0] cadsi[1:0] cadse 111 (0xe5) cadich cadic[15:8] 114 (0xe4) cadicl cadic[7:0] 114 (0xe3) cadac3 cadac[31:24] 114 (0xe2) cadac2 cadac[23:16] 114 (0xe1) cadac1 cadac[15:8] 114 (0xe0) cadac0 cadac[7:0] 114 (0xdf) reserved ? ? ? ? ? ? ? ? (0xde) reserved ? ? ? ? ? ? ? ? (0xdd) reserved ? ? ? ? ? ? ? ? (0xdc) reserved ? ? ? ? ? ? ? ? (0xdb) reserved ? ? ? ? ? ? ? ? (0xda) reserved ? ? ? ? ? ? ? ? (0xd9) reserved ? ? ? ? ? ? ? ? (0xd8) reserved ? ? ? ? ? ? ? ? (0xd7) reserved ? ? ? ? ? ? ? ? (0xd6) reserved ? ? ? ? ? ? ? ? (0xd5) reserved ? ? ? ? ? ? ? ? (0xd4) chgdcsr ? ? ? battpvl chgdisc1 chgdi sc1 chgdif chgdie 131 (0xd3) reserved ? ? ? ? ? ? ? ? (0xd2) bgcsr ? ?bgdbgscde ? ? bgscdif bgscdie 127 (0xd1) bgcrr bgcr[7:0] 126 (0xd0) bgccr ? ? bgcc[5:0] 254 (0xcf) reserved ? ? ? ? ? ? ? ? (0xce) reserved ? ? ? ? ? ? ? ? (0xcd) reserved ? ? ? ? ? ? ? ? (0xcc) reserved ? ? ? ? ? ? ? ? (0xcb) reserved ? ? ? ? ? ? ? ? (0xca) reserved ? ? ? ? ? ? ? ? (0xc9) reserved ? ? ? ? ? ? ? ? (0xc8) rocr rocs ? ?rocd ? ? rocwif rocwie 134 (0xc7) reserved ? ? ? ? ? ? ? ? (0xc6) reserved ? ? ? ? ? ? ? ? (0xc5) reserved ? ? ? ? ? ? ? ? (0xc4) reserved ? ? ? ? ? ? ? ? (0xc3) reserved ? ? ? ? ? ? ? ? (0xc2) reserved ? ? ? ? ? ? ? ? (0xc1) reserved ? ? ? ? ? ? ? ? (0xc0) reserved ? ? ? ? ? ? ? ? 255 8042a?avr?07/09 atmega16hvb/32hvb (0xbf) reserved ? ? ? ? ? ? ? ? (0xbe) twbcsr twbcif twbcie ? ? ? twbdt1 twbdt0 twbcip 187 (0xbd) twamr twam[6:0] ?187 (0xbc) twcr twint twea twsta twsto twwc twen ?twie 184 (0xbb) twdr 2?wire serial interface data register 186 (0xba) twar twa[6:0] twgce 186 (0xb9) twsr tws[7:3] ?twps1twps0 185 (0xb8) twbr 2?wire serial interface bit rate register 184 (0xb7) reserved ? ? ? ? ? ? ? (0xb6) reserved ? ? ? ? ? ? ? ? (0xb5) reserved ? ? ? ? ? ? ? ? (0xb4) reserved ? ? ? ? ? ? ? ? (0xb3) reserved ? ? ? ? ? ? ? ? (0xb2) reserved ? ? ? ? ? ? ? ? (0xb1) reserved ? ? ? ? ? ? ? ? (0xb0) reserved ? ? ? ? ? ? ? ? (0xaf) reserved ? ? ? ? ? ? ? ? (0xae) reserved ? ? ? ? ? ? ? ? (0xad) reserved ? ? ? ? ? ? ? ? (0xac) reserved ? ? ? ? ? ? ? ? (0xab) reserved ? ? ? ? ? ? ? ? (0xaa) reserved ? ? ? ? ? ? ? ? (0xa9) reserved ? ? ? ? ? ? ? ? (0xa8) reserved ? ? ? ? ? ? ? ? (0xa7) reserved ? ? ? ? ? ? ? ? (0xa6) reserved ? ? ? ? ? ? ? ? (0xa5) reserved ? ? ? ? ? ? ? ? (0xa4) reserved ? ? ? ? ? ? ? ? (0xa3) reserved ? ? ? ? ? ? ? ? (0xa2) reserved ? ? ? ? ? ? ? ? (0xa1) reserved ? ? ? ? ? ? ? ? (0xa0) reserved ? ? ? ? ? ? ? ? (0x9f) reserved ? ? ? ? ? ? ? ? (0x9e) reserved ? ? ? ? ? ? ? ? (0x9d) reserved ? ? ? ? ? ? ? ? (0x9c) reserved ? ? ? ? ? ? ? ? (0x9b) reserved ? ? ? ? ? ? ? ? (0x9a) reserved ? ? ? ? ? ? ? ? (0x99) reserved ? ? ? ? ? ? ? ? (0x98) reserved ? ? ? ? ? ? ? ? (0x97) reserved ? ? ? ? ? ? ? ? (0x96) reserved ? ? ? ? ? ? ? ? (0x95) reserved ? ? ? ? ? ? ? ? (0x94) reserved ? ? ? ? ? ? ? ? (0x93) reserved ? ? ? ? ? ? ? ? (0x92) reserved ? ? ? ? ? ? ? ? (0x91) reserved ? ? ? ? ? ? ? ? (0x90) reserved ? ? ? ? ? ? ? ? (0x8f) reserved ? ? ? ? ? ? ? ? (0x8e) reserved ? ? ? ? ? ? ? ? (0x8d) reserved ? ? ? ? ? ? ? ? (0x8c) reserved ? ? ? ? ? ? ? ? (0x8b) reserved ? ? ? ? ? ? ? ? (0x8a) reserved ? ? ? ? ? ? ? ? (0x89) ocr1b timer/counter1 ? output compare register b 95 (0x88) ocr1a timer/counter1 ? output compare register a 95 (0x87) reserved ? ? ? ? ? ? ? ? (0x86) reserved ? ? ? ? ? ? ? ? (0x85) tcnt1h timer/counter1 (8 bit) high byte 95 (0x84) tcnt1l timer/counter1 (8 bit) low byte 95 (0x83) reserved ? ? ? ? ? ? ? ? (0x82) reserved ? ? ? ? ? ? ? ? (0x81) tccr1b ? ? ? ? ? cs12 cs11 cs10 81 (0x80) tccr1a tcw1 icen1 icnc1 ices1 ics1 ? ?wgm10 94 (0x7f) reserved ? ? ? ? ? ? ? ? (0x7e) didr0 ? ? ? ? ? ? pa1did pa0did 122 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 256 8042a?avr?07/09 atmega16hvb/32hvb (0x7d) reserved ? ? ? ? ? ? ? ? (0x7c) vadmux ? ? ? ? vadmux[3:0] 120 (0x7b) reserved ? ? ? ? ? ? ? ? (0x7a) vadcsr ? ? ? ? vaden vadsc vadccif vadccie 120 (0x79) vadch ? ? ? ? vadc data register high byte 121 (0x78) vadcl vadc data register low byte 121 (0x77) reserved ? ? ? ? ? ? ? ? (0x76) reserved ? ? ? ? ? ? ? ? (0x75) reserved ? ? ? ? ? ? ? ? (0x74) reserved ? ? ? ? ? ? ? ? (0x73) reserved ? ? ? ? ? ? ? ? (0x72) reserved ? ? ? ? ? ? ? ? (0x71) reserved ? ? ? ? ? ? ? ? (0x70) reserved ? ? ? ? ? ? ? ? (0x6f) timsk1 ? ? ? ? icie1 ocie1b ocie1a toie1 96 (0x6e) timsk0 ? ? ? ? icie0 ocie0b ocie0a toie0 96 (0x6d) reserved ? ? ? ? ? ? ? ? (0x6c) pcmsk1 pcint[15:8] 60 (0x6b) pcmsk0 ? ? ? ? pcint[3:0] 61 (0x6a) reserved ? ? ? ? ? ? ? ? (0x69) eicra isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 58 (0x68) pcicr ? ? ? ? ? ?pcie1pcie0 60 (0x67) reserved ? ? ? ? ? ? ? ? (0x66) fosccal fast oscillator calibration register 32 (0x65) reserved ? ? ? ? ? ? ? ? (0x64) prr0 ? prtwi prvrm ? prspi prtim1 prtim0 prvadc 40 (0x63) reserved ? ? ? ? ? ? ? ? (0x62) reserved ? ? ? ? ? ? ? ? (0x61) clkpr clkpce ? ? ? ? ? clkps1 clkps0 32 (0x60) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 49 0x3f (0x5f) sreg i t h s v n z c 10 0x3e (0x5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 13 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 13 0x3c (0x5c) reserved ? ? ? ? ? ? ? ? 0x3b (0x5b) reserved ? ? ? ? ? ? ? ? 0x3a (0x5a) reserved ? ? ? ? ? ? ? ? 0x39 (0x59) reserved ? ? ? ? ? ? ? ? 0x38 (0x58) reserved ? ? ? ? ? ? ? ? 0x37 (0x57) spmcsr spmie rwwsb sigrd ctpb rflb pgwrt pgers spmen 206 0x36 (0x56) reserved ? ? ? ? ? ? ? ? 0x35 (0x55) mcucr ? ?ckoepud ? ? ivsel ivce 78/32 0x34 (0x54) mcusr ? ? ? ocdrf wdrf bodrf extrf porf 49 0x33 (0x53) smcr ? ? ? ? sm[2:0] se 39 0x32 (0x52) reserved ? ? ? ? ? ? ? ? 0x31 (0x51) dwdr debugwire data register 190 0x30 (0x50) reserved ? ? ? ? ? ? ? ? 0x2f (0x4f) reserved ? ? ? ? ? ? ? ? 0x2e (0x4e) spdr spi data register 107 0x2d (0x4d) spsr spif wcol ? ? ? ? ?spi2x 106 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 105 0x2b (0x4b) gpior2 general purpose i/o register 2 24 0x2a (0x4a) gpior1 general purpose i/o register 1 24 0x29 (0x49) ocr0b timer/counter0 output compare register b 95 0x28 (0x48) ocr0a timer/counter0 output compare register a 95 0x27 (0x47) tcnt0h timer/counter0 (8 bit) high byte 95 0x26 (0x46) tcnt0l timer/counter0 (8 bit) low byte 95 0x25 (0x45) tccr0b ? ? ? ? ? cs02 cs01 cs00 81 0x24 (0x44) tccr0a tcw0 icen0 icnc0 ices0 ics0 ? ?wgm00 94 0x23 (0x43) gtccr tsm ? ? ? ? ? ? psrsync 0x22 (0x42) eearh ? ? ? ? ? ? eeprom high byte 20 0x21 (0x41) eearl eeprom address register low byte 20 0x20 (0x40) eedr eeprom data register 20 0x1f (0x3f) eecr ? ? eepm1 eepm0 eerie eempe eepe eere 21 0x1e (0x3e) gpior0 general purpose i/o register 0 24 0x1d (0x3d) eimsk ? ? ? ? int3 int2 int1 int0 59 0x1c (0x3c) eifr ? ? ? ? intf3 intf2 intf1 intf0 59 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 257 8042a?avr?07/09 atmega16hvb/32hvb notes: 1. for compatibility with future devices, reserved bits s hould be written to zero if accessed. reserved i/o memory address es should never be written. 2. i/o registers within the address range $00 - $1f are directly bit-accessible using th e sbi and cbi instructions. in these reg - isters, the value of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical o ne to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag r ead as set, thus clearing the fl ag. the cbi and sbi instruction s work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses $00 - $3f must be used. when addressing i/o regis- ters as data space using ld and st instructions, $20 mu st be added to these addresses. the atmega16hvb/32hvb is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the ext ended i/o space from $60 - $ff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 0x1b (0x3b) pcifr ? ? ? ? ? ?pcif1pcif0 60 0x1a (0x3a) reserved ? ? ? ? ? ? ? ? 0x19 (0x39) reserved ? ? ? ? ? ? ? ? 0x18 (0x38) reserved ? ? ? ? ? ? ? ? 0x17 (0x37) osicsr ? ? ? osisel0 ? ? osist osien 33 0x16 (0x36) tifr1 ? ? ? ? icf1 ocf1b ocf1a tov1 96 0x15 (0x35) tifr0 ? ? ? ? icf0 ocf0b ocf0a tov0 96 0x14 (0x34) reserved ? ? ? ? ? ? ? ? 0x13 (0x33) reserved ? ? ? ? ? ? ? ? 0x12 (0x32) reserved ? ? ? ? ? ? ? ? 0x11 (0x31) reserved ? ? ? ? ? ? ? ? 0x10 (0x30) reserved ? ? ? ? ? ? ? ? 0x0f (0x2f) reserved ? ? ? ? ? ? ? ? 0x0e (0x2e) reserved ? ? ? ? ? ? ? ? 0x0d (0x2d) reserved ? ? ? ? ? ? ? ? 0x0c (0x2c) reserved ? ? ? ? ? ? ? ? 0x0b (0x2b) reserved ? ? ? ? ? ? ? ? 0x0a (0x2a) reserved ? ? ? ? ? ? ? ? 0x09 (0x29) reserved ? ? ? ? ? ? ? ? 0x08 (0x28) portc ? ? portc5 portc4 portc3 portc2 portc1 portc0 66 0x07 (0x27) reserved ? ? ? ? ? ? ? ? 0x06 (0x26) pinc ? ? ? pinc4 pinc3 pinc2 pinc1 pinc0 66 0x05 (0x25) portb portb7 portb6 portb 5 portb4 portb3 portb2 portb1 portb0 78 0x04 (0x24) ddrb ddb7 ddb6 ddb 5 ddb4 ddb3 ddb2 ddb1 ddb0 78 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 78 0x02 (0x22) porta ? ? ? ? porta3 porta2 porta1 porta0 78 0x01 (0x21) ddra ? ? ? ? dda3 dda2 dda1 dda0 78 0x00 (0x20) pina ? ? ? ? pina3 pina2 pina1 pina0 78 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 258 8042a?avr?07/09 atmega16hvb/32hvb 35. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp k direct jump pc knone3 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc znone3 call k direct subroutine call pc knone4 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 259 8042a?avr?07/09 atmega16hvb/32hvb brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear ze ro flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 35. instruction set summary (continued) mnemonics operands description operation flags #clocks 260 8042a?avr?07/09 atmega16hvb/32hvb out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a 35. instruction set summary (continued) mnemonics operands description operation flags #clocks 261 8042a?avr?07/09 atmega16hvb/32hvb 36. ordering information 36.1 atmega16hvb speed (mhz) power supply ordering code package operation range 1 - 8 mhz 4 - 25v ATMEGA16HVB-8X3 44x1 -40 c to 85 c package type 44x1 44-lead, 4.4 mm body width, plastic th in shrink small outline package (tssop) 262 8042a?avr?07/09 atmega16hvb/32hvb 36.2 atmega32hvb speed (mhz) power supply ordering code package operation range 1 - 8 mhz 4 - 25v atmega32hvb-8x3 44x1 -40 c to 85 c package type 44x1 44-lead, 4.4 mm body width, plastic th in shrink small outline package (tssop) 263 8042a?avr?07/09 atmega16hvb/32hvb 37. packaging information 37.1 44x1 title drawing no. r rev. n ote: these dra w ings are for general information only. refer to jedec dra w ing mo-153be. 2325 orchard park w ay san jose, ca 95131 5/16/07 44x1 , 44-lead, 4.4 mm body w idth, plastic thin shrink small o u tline package (tssop) 44x1 a common dimen s ion s (unit of meas u re = mm) s ymbol min nom max note a ?? 1.20 a1 0.05 ? b 0.17 ? 0.27 c 0.09 ? 0.20 d 10.90 11.00 11.10 e1 4.30 4.40 4.50 e 6.20 6.40 6.60 e 0.50 typ l 0.50 0.60 0.70 ? 0 o ? 8 o s ide view top view end view ? 1 44 2 3 l c e1 e d e b a a1 0.15 title drawing no. r rev. n ote: these dra w ings are for general information only. refer to jedec dra w ing mo-153be. 2325 orchard park w ay san jose, ca 95131 5/16/07 44x1 , 44-lead, 4.4 mm body w idth, plastic thin shrink small o u tline package (tssop) 44x1 a common dimen s ion s (unit of meas u re = mm) s ymbol min nom max note a ?? 1.20 a1 0.05 ? 0.15 b 0.17 ? 0.27 c 0.09 ? 0.20 d 10.90 11.00 11.10 e1 4.30 4.40 4.50 e 6.20 6.40 6.60 e 0.50 typ l 0.50 0.60 0.70 ? 0 o ? 8 o s ide view top view end view ? 1 44 2 3 l c e1 e d e b a a1 264 8042a?avr?07/09 atmega16hvb/32hvb 38. errata 38.1 atmega16hvb 38.1.1 rev. b no known errata. 38.1.2 rev. a not sampled. 38.2 atmega32hvb 38.2.1 rev. b no known errata. 38.2.2 rev. a not sampled. 265 8042a?avr?07/09 atmega16hvb/32hvb 39. revision history 39.1 rev a 08/09 1. initial revision i 8042a?avr?07/09 atmega16hvb/32hvb table of contents features ................ ................ .............. .............. .............. .............. ............. 1 1 pin configurations ..... ................ ................. ................ ................ ............. 2 1.1tssop ...................................................................................................................... 2 1.2pin descriptions .........................................................................................................2 2 overview ............ ................ ................ .............. .............. .............. ............. 5 2.1comparison between atmega16hvb and atmega32hvb .....................................7 3 disclaimer .............. .............. .............. .............. .............. .............. ............. 8 4 resources .............. .............. .............. .............. .............. .............. ............. 8 5 about code examples . ................. ................ ................ .............. ............. 8 6 data retention .......... ................ ................ ................. ................ ............... 8 7 avr cpu core ................. ................ ................ .............. .............. ............. 9 7.1overview ................................................................................................................... .9 7.2alu ? arithmetic logic unit .....................................................................................10 7.3status register ........................................................................................................10 7.4general purpose register file ................................................................................12 7.5stack pointer ...........................................................................................................13 7.6instruction execution timing ...................................................................................14 7.7reset and interrupt handling ...................................................................................14 8 avr memories .......... ................ ................ ................. ................ ............. 17 8.1overview ..................................................................................................................1 7 8.2in-system reprogrammable flash program memory .............................................17 8.3sram data memory ................................................................................................17 8.4eeprom data memory ..........................................................................................19 8.5i/o memory ..............................................................................................................19 8.6register description ................................................................................................20 9 system clock and clock opti ons ........... ................. ................ ............. 25 9.1clock systems and their distribution .......................................................................25 9.2clock sources .........................................................................................................26 9.3clock startup sequence ..........................................................................................28 9.4clock output ............................................................................................................28 9.5system clock prescaler ..........................................................................................28 ii 8042a?avr?07/09 atmega16hvb/32hvb 9.6vadc clock prescaler ............................................................................................29 9.7osi ? oscillator sampling interface ........................................................................29 9.8register description ................................................................................................32 10 power management and sleep modes ........ ................ .............. ........... 35 10.1sleep modes ..........................................................................................................35 10.2idle mode ...............................................................................................................37 10.3adc noise reduction ............................................................................................37 10.4power-save mode ..................................................................................................37 10.5power-off mode .....................................................................................................38 10.6power reduction register .....................................................................................38 10.7minimizing power consumption ............................................................................38 10.8register description ..............................................................................................39 11 system control and reset .... .............. .............. .............. .............. ........ 42 11.1resetting the avr .................................................................................................42 11.2reset sources .......................................................................................................42 11.3reset and the voltage reference .........................................................................45 11.4watchdog timer ....................................................................................................46 11.5register description ..............................................................................................49 12 interrupts ............... .............. .............. .............. .............. .............. ........... 52 12.1overview ................................................................................................................52 12.2interrupt vectors in atmega16hvb/32hvb ..........................................................52 12.3moving interrupts between application and boot space .......................................56 12.4register description ..............................................................................................56 13 external interrupts .......... ................ ................ .............. .............. ........... 58 13.1overview ................................................................................................................58 13.2register description ..............................................................................................58 14 high voltage i/o ports ............... ................. ................ ................ ........... 62 14.1overview ................................................................................................................62 14.2high voltage ports as general digital i/o .............................................................63 14.3overview ................................................................................................................64 14.4alternate port functions ........................................................................................64 14.5register description ..............................................................................................66 15 low voltage i/o-ports ......... .............. .............. .............. .............. ........... 67 15.1overview ................................................................................................................67 iii 8042a?avr?07/09 atmega16hvb/32hvb 15.2low voltage ports as general digital i/o ..............................................................68 15.3alternate port functions ........................................................................................72 15.4register description ..............................................................................................78 16 timer/counter0 and timer/counter1 pr escalers .............. ............ ...... 79 16.1overview ................................................................................................................79 16.2external clock source ...........................................................................................80 16.3register description ..............................................................................................81 17 timer/counter (t/c0,t/c1) .. .............. .............. .............. .............. ........... 82 17.1features ................................................................................................................82 17.2overview ................................................................................................................82 17.3timer/counter clock sources ...............................................................................83 17.4counter unit ..........................................................................................................83 17.5modes of operation ...............................................................................................84 17.6input capture unit .................................................................................................86 17.7output compare unit .............................................................................................88 17.8timer/counter timing diagrams ...........................................................................89 17.9accessing registers in 16-bit mode ......................................................................90 17.10register description ............................................................................................94 18 spi ? serial peripheral in terface ................ ................ ................ ........... 98 18.1features ................................................................................................................98 18.2overview ................................................................................................................98 18.3ss pin functionality ............................................................................................103 18.4data modes .........................................................................................................103 18.5register description ............................................................................................105 19 coulomb counter - dedicated fuel gauging sigma-delta adc ...... 108 19.1features ..............................................................................................................108 19.2overview ..............................................................................................................108 19.3normal operation ................................................................................................109 19.4regular current detection operation ..................................................................110 19.5offset canceling by polarity switching ................................................................110 19.6configuration and usage .....................................................................................111 19.7register description ............................................................................................111 20 voltage adc ? 7-channel general purpose 12-bit sigma-delta adc 117 20.1features ..............................................................................................................117 iv 8042a?avr?07/09 atmega16hvb/32hvb 20.2overview ..............................................................................................................117 20.3operation .............................................................................................................117 20.4register description ............................................................................................120 21 voltage reference and temperature sensor ............. .............. ......... 123 21.1features ..............................................................................................................123 21.2overview ..............................................................................................................123 21.3operation .............................................................................................................124 21.4bandgap calibration ............................................................................................124 21.5bandgap buffer settling time ..............................................................................125 21.6register description ............................................................................................126 22 charger detect ...... ................. ................ ................ ................. ............. 129 22.1features ..............................................................................................................129 22.2overview ..............................................................................................................129 22.3operation .............................................................................................................130 22.4register description ............................................................................................131 23 voltage regulator ............. .............. .............. .............. .............. ........... 132 23.1features ..............................................................................................................132 23.2overview ..............................................................................................................132 23.3regulator start-up ...............................................................................................133 23.4battery pack short detection ..............................................................................133 23.5black-out detection .............................................................................................133 23.6register description ............................................................................................134 24 battery protection ............. .............. .............. .............. .............. ........... 135 24.1features ..............................................................................................................135 24.2overview ..............................................................................................................135 24.3operation .............................................................................................................136 24.4external protection input .....................................................................................137 24.5optimizing usage for low power consumption ..................................................139 24.6battery protection cpu interface ........................................................................140 24.7register description ............................................................................................140 25 fet driver ............ .............. .............. .............. .............. .............. ........... 148 25.1features ..............................................................................................................148 25.2overview ..............................................................................................................148 25.3operation and usage ..........................................................................................149 v 8042a?avr?07/09 atmega16hvb/32hvb 25.4register description ............................................................................................153 26 cell balancing .......... ................ ................ ................. ................ ........... 154 26.1overview ..............................................................................................................154 26.2register description ............................................................................................155 27 2-wire serial interface ....... .............. .............. .............. .............. ........... 156 27.1features ..............................................................................................................156 27.2two-wire serial interface bus definition ..............................................................156 27.3data transfer and frame format ........................................................................157 27.4multi-master bus systems, arbitration and synchronization ...............................160 27.5overview of the twi module ...............................................................................162 27.6using the twi ......................................................................................................165 27.7transmission modes ...........................................................................................168 27.8multi-master systems and arbitration ..................................................................181 27.9bus connect/disconnect for two-wire serial interface .......................................183 27.10register description ..........................................................................................184 28 debugwire on-chip debug s ystem ............. .............. .............. ......... 189 28.1features ..............................................................................................................189 28.2overview ..............................................................................................................189 28.3physical interface ................................................................................................189 28.4software break points .........................................................................................190 28.5limitations of debugwire ...................................................................................190 28.6register description ............................................................................................190 29 boot loader support ? read-while- write self-programming ......... 191 29.1features ..............................................................................................................191 29.2overview ..............................................................................................................191 29.3application and boot loader flash sections .......................................................191 29.4read-while-write and no read-while-write flash sections ..............................192 29.5boot loader lock bits .........................................................................................194 29.6entering the boot loader program ......................................................................195 29.7addressing the flash during self-programming .................................................196 29.8self-programming the flash ................................................................................197 29.9register description ............................................................................................206 30 memory programming ........... ................ ................ ................. ............. 208 30.1program and data memory lock bits .................................................................208 vi 8042a?avr?07/09 atmega16hvb/32hvb 30.2fuse bits ..............................................................................................................209 30.3signature bytes ...................................................................................................210 30.4calibration bytes .................................................................................................211 30.5page size ............................................................................................................211 30.6serial programming .............................................................................................211 30.7parallel programming ..........................................................................................216 31 operating circuit ............. ................ .............. .............. .............. ........... 225 32 electrical characteristics .. ............. .............. .............. .............. ........... 228 32.1absolute maximum ratings* ...............................................................................228 32.2supply current characteristics ............................................................................228 32.3nfet driver characteristics ................................................................................229 32.4reset characteristics ..........................................................................................230 32.5voltage regulator characteristics .......................................................................230 32.6voltage reference and temperature sensor characteristics ..............................230 32.7adc characteristics ............................................................................................231 32.8clock characteristics ...........................................................................................232 32.9cell balancing characteristic ...............................................................................233 32.10battery protection characteristics .....................................................................233 32.11external interrupt characteristics ......................................................................233 32.12general i/o lines characteristics ......................................................................234 32.132-wire serial interface characteristics ...............................................................235 32.14spi timing characteristics ................................................................................236 32.15serial programming characteristics ..................................................................237 32.16parallel programming characteristics ...............................................................238 33 typical characteristics ....... .............. .............. .............. .............. ......... 241 33.1supply current characteristics ............................................................................241 33.2nfet driver characteristics ................................................................................246 33.3battery protection characteristics .......................................................................248 33.4clock characteristics ...........................................................................................248 33.5voltage reference characteristics .......................................................................250 33.6voltage regulator characteristics ........................................................................251 33.7bod threshold characteristics ............................................................................253 34 register summary ............ .............. .............. .............. .............. ........... 254 35 instruction set summary .... .............. .............. .............. .............. ......... 258 vii 8042a?avr?07/09 atmega16hvb/32hvb 36 ordering information .......... .............. .............. .............. .............. ......... 261 36.1atmega16hvb ....................................................................................................261 36.2atmega32hvb ....................................................................................................262 37 packaging information .......... ................ ................ ................. ............. 263 37.144x1 ....................................................................................................................26 3 38 errata ........... ................ ................ ................. ................ .............. ........... 264 38.1atmega16hvb ....................................................................................................264 38.2atmega32hvb ....................................................................................................264 39 revision history ....... ................ ................ ................. ................ ........... 265 39.1rev.d - 05/09 ......................................................................................................265 39.2rev.c - 03/09 ......................................................................................................265 39.3rev.b - 01/09 .......................................................................................................266 39.4rev.a - 11/08 .......................................................................................................267 table of contents.......... ................. ................ ................ ................. ........... i 8042a?avr?07/09 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (852) 2245-6100 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support avr@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ? 2009 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, avr ? and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. table of contentsi |
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